Reliable memory chips improve neural network accuracy in edge devices
ReSAFT: An Efficient Stuck-at Fault-Tolerant Scheme for ReRAM-based Process-in-Memory Accelerators
Hardware Architecture
Summary
ReRAM memory chips help computers run neural networks more quickly and use less energy, but sometimes parts of these chips get stuck and cause errors that reduce accuracy. The authors created a system that adds extra memory rows and columns along with a smart way to place data in the chips to fix these stuck errors with minimal extra cost. Their method recovers much of the lost accuracy and greatly extends how long the chips work correctly. This makes using these memory chips in important applications more reliable.
What this means in practice
- •For hardware engineers: Design ReRAM-based accelerators with improved fault tolerance to sustain CNN inference accuracy under permanent memory faults.
- •For embedded system developers: Develop energy-efficient edge devices executing neural network tasks reliably despite hardware defects in memory arrays.
Authors
Aniseh Dorostkar, Hamed Farbeh, Hamid R. Zarandi
Abstract
Analog ReRAM-based process-in-memory (PIM) accelerators provide high parallelism and energy efficiency for deep convolutional neural networks (CNNs) inference. However, their susceptibility to permanent faults, such as stuck-at high (SaH) and stuck-at low (SaL) resistance states, poses a major challenge by permanently corrupting the CNN weights mapped to conductance values of ReRAM cells and degrading inference accuracy, which leads to system unreliability in safety-critical applications. In this paper, we propose a fault-tolerant scheme for analog ReRAM-based PIM accelerators to tackle stuck-at faults (SAFs) with minimal redundancy overhead to recover classification accuracy degradation. The proposed scheme contains a redundancy-based hardware solution alongside fault-aware mapping method for ensuring reliable analog computation in ReRAM crossbar. We analyze the impact of varying number of redundant rows and columns on accuracy and design metrics. Subsequently, a multi-objective optimization (MOO) problem is formulated and solved to efficiently determine the number of redundant rows and columns, considering trade-offs among various design metrics. Furthermore, a fault-aware weight mapping is proposed for dual-crossbar structures to further compensate for the accuracy degradation caused by SAFs. Simulation results show that, for the SimpleNet model using the MNIST dataset, the inference accuracy is recovered by approximately 22.39%, on average, across four configurations of optimal solutions, each offering a trade-off between reliability and area, energy consumption, and latency overheads. The mean-time-tofailure (MTTF) improves by about 61x on average compared to the baseline. These selected configurations also reduce energy and area overheads by 32%, on average, in comparison to row-only and column-only configurations.