CircuitGate improves logic circuit modeling across diverse datasets
CircuitGate: Logic-Consistent Circuit-Level Functional Modeling for And-Inverter Graphs
Machine Learning
Summary
Digital circuits are often represented as networks of simple logic gates called And-Inverter Graphs (AIGs). Existing methods to analyze these networks mostly look at individual gates and their immediate connections, which misses the bigger picture of how the entire circuit behaves. The authors created CircuitGate, a new way to understand these circuits by considering how whole sections work together, improving accuracy in identifying equivalent gates and predicting signal behavior. Their approach generalizes well across different datasets, showing promise for better logic design and verification.
What this means in practice
- •For chip design engineers: Identify equivalent logic gates more accurately to simplify circuit designs and verify correctness in complex digital systems.
- •For hardware verification teams: Predict signal probabilities in digital circuits to improve error detection and functional validation during hardware testing.
Authors
Qifan Zhang, Ruijie Li, Fangzhou Zhang, Qian Ma, Hui Li, Furui Zhan, Yongpeng Wang, Liying Hao, Shikai Guo
Abstract
And-Inverter Graphs (AIGs) are fundamental representations for logic synthesis and verification in Electronic Design Automation (EDA). As structured representations of complex digital systems, AIGs require models to capture functional dependencies beyond local structure and remain robust to functionality-preserving transformations. In learning-based AIG representation, existing approaches are predominantly based on GNNs and rely on local gate-level message passing, limiting their ability to capture circuit-level functional context and making the learned representations sensitive to topology-specific patterns. Therefore, we propose CircuitGate, a function-aware AIG representation learning framework that advances from gate-level semantics to circuit-level functional modeling. CircuitGate explicitly encodes global primary-input (PI) support and models support-overlap-aware reconvergence between fanins, while incorporating logic-inspired Boolean constraints to encourage functionally consistent representations. We evaluate CircuitGate on the large-scale ForgeEDA benchmark and further validate it on the EPFL and ITC'99 benchmarks. Across equivalent-gate identification and signal-probability prediction tasks, CircuitGate consistently outperforms existing methods, achieving up to 21.7% and 14.2% reductions in MAE, respectively. Under direct ForgeEDA-to-OpenABC transfer without fine-tuning, CircuitGate also achieves the best equivalent-gate identification performance, demonstrating strong cross-dataset generalization. These results demonstrate the effectiveness of modeling circuit-level functional dependencies beyond local topology.