VTen boosts verification speed and cuts code for hardware accelerators
vTen: Tensor-Centric Verification Framework for Domain-Specific Accelerators
Distributed, Parallel, and Cluster ComputingHardware Architecture
Summary
Verifying specialized computer chips called Domain-Specific Accelerators (DSAs) is usually slow and complicated because software tests and hardware checks don’t communicate efficiently. The authors introduce vTen, a new framework that separates what the tests should do from how they run, using a simple language and grouping operations together. This approach reduces the time spent waiting for communication by half and makes the test code much simpler. They tested vTen on a real 3D U-Net accelerator and found both faster verification and cleaner code.
What this means in practice
- •For hardware verification engineers: Reduce simulation time and simplify testing code for domain-specific chip designs to improve verification productivity.
- •For ai hardware designers: Accelerate validation cycles of AI accelerators by efficiently mapping software tensor operations to hardware simulation tests.
Authors
Chanmin Baek, Keehyuk Lee, Mincheol Cha, Somi Hong, Xuan Truong Nguyen, Hyuk-Jae Lee
Abstract
The semantic gap between tensor-centric software models and signal-level hardware testbenches creates significant productivity bottlenecks in verifying Domain-Specific Accelerators (DSAs). Existing frameworks like Cocotb suffer from prohibitive synchronization overheads due to fine-grained interactions. To address this, we propose vTen, a data-centric framework that strictly decouples verification intent from execution mechanics. By leveraging a declarative DSL and kernel-granular batching, vTen minimizes host-simulator interaction frequency. Evaluation on a production-scale 3D U-Net accelerator demonstrates that vTen achieves a 2x performance improvement in simulation latency and a 60.3% reduction in code complexity compared to Cocotb.