BrainScaleS system estimates synapse loss in neuromorphic chips
Synapse Loss Estimation for the BrainScaleS Wafer-scale Neuromorphic System
Emerging TechnologiesNeural and Evolutionary Computing
Summary
Neuromorphic computers combine memory and processing like the brain to run simulations faster and use less energy. The BrainScaleS system is one such chip that can connect neurons flexibly. The authors studied how often these chips fail to provide enough synapse connections for certain brain network models, causing some synapses to be lost. They developed a way to predict this loss and tested it on real hardware mappings to show how well the system handles different network sizes and densities.
What this means in practice
- •For neuromorphic hardware engineers: Optimize hardware and network model settings to minimize synapse loss when mapping onto BrainScaleS neuromorphic chips.
- •For neuromorphic software developers: Benchmark and improve mapping software that assigns neural network models to BrainScaleS hardware for better resource utilization.
Authors
Bernhard Vogginger, Christian Mayr
Abstract
Neuromorphic hardware combines memory (synapses) and computation (neurons) into the same silicon substrate to avoid the von-Neumann bottleneck. This way, neuromorphic computing aims to make computational neuroscience simulations and AI processing faster and more energy-efficient. The common crossbar architecture integrates a synapse matrix (analog, mixed-signal or digital) with a neuron array into a neurosynaptic core, whereas multiple cores are interconnected via a dedicated spike routing network. One of such neuromorphic architecture is the BrainScaleS wafer-scale system which allows the realization of very flexible network architecture, supporting both dense and sparse connectivity by highly configurable neurosynaptic cores. Yet, when network models from computational neuroscience are mapped to the BrainScaleS wafer, synapse loss can occur which means that for some model synapses no hardware synapse is available due to the restricted connectivity of the hardware. In this work we analyze the synapse loss when mapping uniform random networks to BrainScaleS both theoretically and empirically. We first develop a methodology to estimate maximum-sized networks without synapse loss based on probability distributions and the hardware's synapse routing architecture. Next, we adopt the methodology to predict the synapse loss for denser or larger network models. Then, we compare the predictions with results from actual runs of the mapping software: The results show the capabilities and limitations of the BrainScaleS system itself and spot shortcomings of the current mapping algorithms. The developed methodology can be helpful in multiple ways: to find the optimal settings when mapping a given network model to BrainScaleS, to act as a benchmark for the mapping software, and as tool for design space exploration for new hardware.