SparseCraft improves sparse accelerator performance and efficiency
SparseCraft: Agentic Hardware-Software Co-Optimization for Sparse Computing
Hardware ArchitectureArtificial Intelligence
Summary
Sparse accelerators help computers run sparse data calculations more efficiently, but designing them is complex and often relies on guesses rather than real hardware tests. The authors created SparseCraft, a system that uses a language model to continuously edit and test hardware designs based on actual measurements, making improvements step-by-step. This approach led to big reductions in processing time, memory traffic, and chip area when tested on a common sparse deep learning task. The model even generated new hardware components to save energy, showing that combining software and hardware changes can create better specialized chips.
What this means in practice
- •For hardware design engineers: Automate iterative hardware-software design for sparse accelerators using measured outcomes to improve efficiency and performance.
- •For embedded systems developers: Create energy-efficient sparse neural network processors by leveraging co-optimized memory and kernel scheduling guided by language models.
Authors
Rajatabha Chakraborty, M P Samartha, Vedant Pahariya, Priyesh Shukla
Abstract
Sparse-accelerator design spaces are usually searched against analytical models, so a design point is admitted on what a model predicts rather than on what the hardware does. SparseCraft closes that gap with a language model inside a closed CHIA loop. In each of 15 iterations the model reads the measured outcome of the previous one and edits the Chisel RTL, the memory configuration and the sparse-kernel schedule of a Gemmini accelerator through MCP tool servers, and no candidate counts until it has been checked for legality, elaborated, simulated cycle-accurately, checked bit-for-bit on every output against a golden reference, and synthesised. The harness turns each measurement into the next work order, a diagnosed bottleneck with matching strategy guidance, the history of tried designs and a score of the model's own prediction, and a second model repairs changes that fail a gate. On a $512 \times 512$ GraphChallenge sparse-DNN layer the loop reaches 2.1x fewer cycles, 9.8x less off-chip traffic and 22.8% less area than the block-sparse Gemmini baseline, with 5.61x higher modelled perf/W and 11.8x lower EDP. The levers span three layers: a schedule that keeps the dense operand resident removes 9.8x of the traffic, a zero-gated MAC and a zero-row skip unit that the model wrote in Chisel cut energy, and resizing the memories cuts area.