Framework automates stealthy hardware trojan insertion in circuits
CITADEL: CWE-Guided Insertion of Hardware Trojans via Analysis of DFG-Enabled LLMs
Cryptography and Security
Summary
Hardware Trojans are hidden malicious modifications inside computer chips that can cause serious security problems. Creating realistic examples of these Trojans is hard because it requires detailed manual work. The authors developed a system called CITADEL that uses AI language models and circuit analysis to automatically find weaknesses and insert Trojans in hardware designs. Their system makes Trojans that are small, hard to detect, and only activate under rare conditions. This helps researchers create better tests for hardware security.
What this means in practice
- •For hardware security teams: Create realistic hardware Trojan examples to evaluate and improve chip security testing methods.
- •For integrated circuit designers: Identify likely hardware vulnerabilities by analyzing module contexts for more secure design and verification.
Authors
Jayanth Thangellamudi, Raghul Saravanan, Sudipta Paria, Swarup Bhunia, Sai Manoj P D
Abstract
The increasing sophistication of Hardware Trojans (HTs) and system-level vulnerabilities poses significant risks to modern integrated circuits. However, constructing realistic HT scenarios, remains a substantial burden: researchers must manually analyze complex RTL structures, identify plausible weaknesses, and craft stealthy, synthesizable insertions that preserve functional correctness. This paper introduces CITADEL CWE-Guided Insertion of Trojans via Analysis of DFG-Enabled LLMs, a framework that leverages Large Language Models (LLMs) and Data Flow Graphs (DFGs) to automate CWE-grounded HT synthesis. CITADEL uses structured CWE semantics together with DFG-derived structural context to assist the user in identifying relevant vulnerabilities, localize the module surrounding the chosen insertion point, and perform intent-conditioned RTL modification. The framework produces minimal, synthesizable, and interface-preserving HTs with ultra-rare triggers. Experimental evaluation across diverse RTL designs demonstrates that all generated HTs are 100% syntactically correct, remain undetectable under large-scale random simulation, and are functionally triggerable under their intended activation conditions. These results highlight CITADEL as a scalable and principled method for generating realistic HT benchmarks.