CGRAs get faster by linking loops and pipelining better
CONFERM: Recurrence-Aware Temporal Mapping for Multi-Cycle Multi-Context CGRAs
Hardware Architecture
Summary
Some computer chips called CGRAs process tasks that include loops and slow operations, which can limit their speed. The authors introduce CONFERM, a method that coordinates how loops and slow operations are scheduled together, allowing the chip to do several parts of a loop at once more efficiently. This method shortens the time between starting tasks and reduces the resources needed, leading to more than double the speed on tested examples. CONFERM also finds these schedules faster than previous methods.
What this means in practice
- •For hardware accelerator developers: Improve scheduling algorithms in CGRAs to boost throughput for DSP and machine learning tasks by better handling loop dependencies and long-latency compute nodes.
- •For embedded systems engineers: Implement CONFERM-inspired scheduling techniques to reduce configuration overhead and increase execution speed in custom CGRA designs used for real-time processing.
Authors
Jun Yin, Jannes Willemen, Stef Cuyckens, Chao Fang, Marian Verhelst
Abstract
Throughput in DSP and machine learning workloads is often limited by two temporal structures, i.e., loop-carried recurrences and long-latency, multi-cycle compute nodes. On spatio-temporal coarse-grained reconfigurable arrays (CGRAs), both bottlenecks can be addressed by overlapping iterations across the multi-context modulo configurations. Yet, existing CGRA mappers schedule a fixed dataflow graph (DFG) that treats recurrence-aware scheduling and operator-level pipelining separately, limiting inter-iteration overlap and inflating routing pressure. To tackle this, we present CONFERM, a recurrence-aware temporal mapper that uses the dominant temporal con-straint to guide the DFG representation and expose opportunities for loop-carried pipelining. CONFERM identifies and prioritizes bottleneck regions during scheduling. The regular loop-carried offsets across interleaved iterations allow the emitted control sequence to repeat at a shorter cadence than the original initiation interval, thus delivering higher throughput with lower CGRA configuration overhead. Across ten benchmark kernels, CONFERM improves throughput by 2.18x over state-of-the-art mappers. Its uniform iteration offsets shorten the emitted initiation interval by 46%. CONFERM's mapper pass also converges faster by 5.07x on average with the same heuristic mapper backend.