Timing aware local logic remapping improves circuit performance after placement
Timing-Driven Logic Remapping with Local Physical Context
Hardware Architecture
Summary
The speed of a computer chip depends on both the way its logic is designed and how the components are physically arranged. When designers try to improve the chip's timing after placing the components, they need to carefully consider the surrounding wiring and loads. The authors developed a new method that looks at small parts of the chip, evaluates different logic options based on estimated locations and wiring delays, and picks the best versions that fit well physically. This approach helps find real timing improvements by combining design changes with physical layout feedback in a smart and systematic way.
What this means in practice
- •For chip design engineers: Improve critical timing on integrated circuits by locally reoptimizing logic after placement using physical feedback.
- •For hardware verification teams: Validate timing improvements by integrating logic remapping with physical layout and routing parasitic analysis.
Authors
Zijian Jiang, Hongyang Pan, Cunqing Lan, Keren Zhu
Abstract
The timing behavior of a mapped circuit depends on both its logic implementation and the physical environment in which that implementation is realized. Revisiting mapping decisions after placement therefore requires a search procedure that accounts for surrounding timing constraints, fanout loads, and interconnect effects. We study local remapping in this setting and develop a framework that couples discrete mapping search with physical implementation feedback. Timing-critical regions are isolated through bounded windows whose interfaces retain the context of the surrounding circuit. Within each window, a mixed-integer formulation jointly selects logic cuts, signal polarities, and library cells under a delay model informed by estimated locations and interconnect parasitics. A continuous relaxation filters the search space before discrete optimization produces alternative implementations with similar modeled timing and different structural choices. These implementations are reconstructed and assessed through legalization, routing-based parasitic estimation, and timing analysis. Physically validated improvements are incorporated into the design, and the updated context guides subsequent searches. The framework provides a systematic way to revisit local logic implementations while accounting for their interaction with an existing placement.