Multi-wire SPI interface boosts data transfer for wearable ultrasound devices
Open-Source Multi-Wire SPI Readout for Wearable Ultrasound Probes
Hardware Architecture
Summary
Wearable ultrasound devices need to send lots of data quickly without using too much power or space. The authors identify a slow step in how data moves inside these devices. They design a new data interface that uses multiple wires to send more data faster, while still working with existing device parts. Tests showed it works well and can handle high speeds, helping future devices transfer ultrasound data more efficiently. They also made their designs freely available for others to use and improve.
What this means in practice
- •For embedded systems engineers: Build wearable ultrasound devices with faster data links between sensors and controllers using a compatible multi-wire SPI interface.
- •For fpga developers: Integrate and test higher bandwidth SPI readout interfaces on FPGA platforms to improve data throughput in compact medical devices.
Authors
Federico Villani, Soumyo Bhattacharjee, Lisa Odermatt, Cédric Hirschi, Luca Benini, Andrea Cossettini
Abstract
Wearable ultrasound probes must transfer increasingly large acquisition payloads while maintaining compact, low-power electronics. In TinyProbe, the current bottleneck in data transfer occurs between the acquisition FPGA and the wireless system controller. This work presents an open-source, multi-wire SPI readout interface that uses serial command and address phases followed by a build-time-selectable dual- or quad-lane payload phase that is intended to address this bottleneck by increasing the potential bandwidth over the wifi limit while retaining compatibility with the Microcontroller-centric wearable US architecture. The interface emulates a serial flash memory, enabling compatibility with a broad range of microcontroller families and their existing peripheral interfaces. On the FPGA, the data path connects the existing acquisition FIFOs to the SPI interface through clock-domain crossing, sample reshaping, and packing into 32-bit words. Dual-SPI readout is integrated into the existing IGLOO2/SiWG917 TinyProbe architecture and verified at an SCLK frequency of 5 MHz. A separate Kria K26 testbed is used to characterize the FPGA SPI interface independently of the acquisition and wireless subsystems, demonstrating error-free transfers at SCLK frequencies up to 66 MHz. These measurements identify the SiWG917 multi-lane SPI implementation as the next bandwidth-limiting component and motivate a future upgrade of the system controller. The HDL and MCU implementations are released under a permissive open-source license.