Open-source chip design for synchronized 8-channel ultrasound transmitters
U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
Hardware Architecture
Summary
Ultrasound machines use tiny probes that send sound pulses from multiple points at once, but many small devices use limited or unchangeable parts for this. The authors created U-Sonic, a chip design that can send controlled ultrasound signals from up to 16 channels, and they tested it to make sure it works well. This design is open for anyone to use and modify, providing more flexibility and easier development of ultrasound devices. Their work shows a way to build better miniature ultrasound transmitters in hardware that fits in small chips.
What this means in practice
- •For medical device builders: Build miniaturized ultrasound probes with flexible, programmable transmitters supporting up to 16 channels based on an open-source chip design.
- •For hardware designers: Integrate an open-source ultrasound transmitter peripheral into custom RISC-V SoC designs to enable synchronized multi-channel ultrasound signal generation.
Authors
Federico Villani, Nico Canzani, Marc-André Wessner, Philippe Sauter, Enrico Zelioli, Andrea Cossettini, Christoph Leitner, Luca Benini
Abstract
Miniaturized ultrasound (US) probes require programmable and synchronized transmit (TX) excitation across multiple elements, while existing compact platforms often rely on limited microcontroller (MCU) pulse generators or closed-source fixed-function pulser devices. We present U-Sonic, an open-source digital US TX peripheral integrated into a 32-bit RISC-V system-on-chip (SoC). The implemented SoC integrates 8 pulser cores, while the parameterized architecture supports up to 16 channels. Each core generates single- or dual-tone bursts with programmable period, duty cycle, pulse count, polarity, and idle level, together with optional inverted stop pulses for active damping. A shared memory-mapped Open Bus Interface (OBI) enables synchronous start and stop of arbitrary channel subsets and supports composite bipolar, gated, and three-level excitation schemes. Functional correctness was verified in Verilator against a Python golden model over 4379 checked cycles across directed and randomized configurations, and confirmed on a Terasic DE10-Lite field-programmable gate array (FPGA). The design was synthesized and placed-and-routed in IHP 130 nm. The post-layout area in kilo gate equivalents (kGE), scales as 1.65 kGE plus 1.66 kGE per channel. The 8-channel instance occupies 14.9 kGE, corresponding to approximately 14.3% of the 104 kGE SoC. The register-transfer level (RTL), register descriptions, verification collateral, and software support are released as open source.