Stella chip speeds up complex machine learning calculations efficiently
STELLA: A 16nm Spatio-Temporal Elastic Low-Latency CGRA for Multi-Stage Pipelined Applications
Hardware Architecture
Summary
Some advanced machine learning tasks, like special math functions and convolutions, need fast and energy-saving hardware beyond the usual designs. The authors built Stella, a new type of chip that flexibly reuses data across time and space to run these tasks quickly. Stella works at high speed with low delay and can perform much better than previous similar chips. This makes it helpful for running newer machine learning methods that aren't just about matrix multiplication.
What this means in practice
- •For hardware engineers: Design hardware accelerators optimized for emerging non-matrix machine learning kernels needing low latency and energy efficiency.
- •For embedded system developers: Integrate efficient spatio-temporal reconfigurable arrays to boost performance in edge devices running diverse ML workloads.
Authors
Jun Yin, Chao Fang, Ryan Antonio, Xiaoling Yi, Yunhao Deng, Fanchen Kong, Marian Verhelst
Abstract
Emerging non-matrix ML kernels, such as LayerNorm, GeLu, FFT or circular convolutions, demand low-latency, energy-efficient spatial accelerators beyond MatMul-centric arrays. STELLA presents a spatio-temporal elastic 16 nm coarse-grained reconfigurable array (CGRA) with a rapid configuration path, per-PE hardware loop control, and a low-latency, deeply pipelined elastic fabric with spatio-temporal data reuse. STELLA reaches up to 110 GOPS/mm2 at 850 MHz, and improves effective kernel throughput by 4.84-7.14x over baseline CGRAs.