Coarse to fine chip layout reduces wiring length up to 18 percent
Coarse-to-Fine Macro Placement via Evolutionary Search and Critical Macro Tuning
Hardware Architecture
Summary
Placing big blocks called macros on a computer chip is important because it affects how well the chip works later. The authors created a new method called C2FPlace that starts by roughly arranging macros and then carefully fine-tunes their positions. This method uses a mix of trial and error with smart selection to explore many placement options and then makes small moves to improve wiring length. Their tests show that C2FPlace can cut the total wiring length by nearly 18% compared to other methods, which helps chips perform better and use less power.
What this means in practice
- •For chip layout engineers: Improve chip designs by reducing wiring lengths with an evolutionary search and refinement approach for macro placement.
- •For electronic design automation (eda) tool developers: Integrate coarse-to-fine macro placement techniques to enhance chip physical design automation software for better layout quality.$Commercial implications: Enables development of advanced EDA tools with better macro placement accuracy and layout optimization, appealing to chip manufacturers.
Authors
Biao Liu, Zhiping Jin, Kaixuan Sun, Zengrui Lu, Qingquan Zhang, Bo Yuan
Abstract
Macro placement is a critical stage in chip physical design that substantially affects downstream implementation quality. Recent search-based methods improve existing layouts through partial reconstruction, but quality-biased or spatially restricted macro selection can limit the diversity of reconstruction proposals, potentially hindering escape from local optima. Moreover, coarse-grid representations restrict placement precision. To address these challenges, we propose C2FPlace, a \textbf{C}oarse-to-\textbf{F}ine macro \textbf{Place}ment framework that integrates population-based evolutionary search with fine-grained refinement. During coarse-grained optimization, tournament selection chooses promising parents from randomly sampled groups of layouts, and stochastic partial rip-up and re-place generates offspring by sampling macro subsets across the entire layout. A two-phase schedule samples reconstruction ratios from a higher range early in the search and a lower range later, supporting broad exploration followed by more conservative refinement. During fine-grained optimization, critical macro tuning enables positional adjustments beyond the coarse grid to obtain additional half-perimeter wirelength (HPWL) reduction. Experiments on the ISPD2005 benchmark show that C2FPlace reduces HPWL by 17.82\% over EGPlace and 17.86\% over RollPlace on average. On the ICCAD2025 benchmark, C2FPlace achieves the best average ranking among the compared methods under the evaluated power, performance, and area (PPA) metrics. Our codes are available in \href{https://github.com/lxxxxb/C2FPlace}{https://github.com/lxxxxb/C2FPlace}.