Chip placement experts speed design by reusing validated policies
CARVE: Breaking Data Barriers in Chip Placement by Harnessing Reusable Expertise
Machine Learning
Summary
Placing components on computer chips efficiently is tough and usually takes a lot of repeated work for each new design. The authors introduce a way to remember and reuse helpful placement strategies from past designs without retraining from scratch each time. Their system checks if an existing strategy can work for a new chip, and only trains new ones when necessary, saving time while keeping good performance. This approach works well on real chip examples and reduces training time by over half.
What this means in practice
- •For chip design engineers: Reuse validated component placement strategies to speed up new chip floorplanning without extensive retraining.
- •For robotics developers: Accelerate learning of navigation policies by reusing and validating existing skill modules in similar environments.
Authors
Jiefu Zhang, Haixiang Sun, Yang Xu, Vaneet Aggarwal, Zishen Wan
Abstract
Pretrained macro-placement policies can reduce repeated optimization across circuits, but deployment often exposes them to unfamiliar designs when the original training data are unavailable. Repeatedly fine-tuning a single serving model can overwrite earlier improvements, while simply saving checkpoints does not determine where they can be reliably reused. We introduce Continual Adaptation through the Reuse of Validated Expertise (CARVE), a framework that represents accumulated expertise as a frozen base policy, immutable specialists, and task-specific credentials obtained through local validation. For a new task, CARVE first checks existing specialists and trains a new specialist from the frozen base only when none qualifies. Under fixed task distributions and validation rules that control cumulative error, we establish expected-performance guarantees for repeated reuse. For bounded losses, we also derive matching worst-case bounds on the local samples needed for reliable reuse. In macro placement, a reuse-first follow-up reduces recorded training time by 58.5% (9.66 to 4.01 hours), while mean HPWL gain changes only from 8.41% to 7.86%. In a simulated receiving deployment, imported specialists are reused on six of seven new IBM circuits with no receiver-side training, achieving a 5.76% mean HPWL gain. Navigation studies provide complementary evidence on repair retention and repeated adaptation.