Hardware accelerator speeds up postquantum signature on edge devices
Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices
Cryptography and SecurityHardware Architecture
Summary
Quantum computers can break existing encryption methods, so new types of cryptography are needed. The Falcon digital signature is one such method but is hard to run on small devices because it relies on complex math usually done by floating-point hardware. The authors developed Peregrino, a complete hardware accelerator built from scratch that can perform the entire Falcon signature process efficiently on devices without floating-point units. Peregrino uses fewer hardware resources than previous designs and runs much faster by emulating floating-point operations in hardware.
What this means in practice
- •For embedded systems engineers: Implement secure post-quantum digital signatures on resource-limited edge devices using efficient and complete hardware acceleration.
- •For cryptographic hardware designers: Design compact Falcon signature accelerators that fit on single FPGAs without native floating-point support, reducing resource needs and improving performance.
Authors
Antonio Carreño, Jaime Señor, Jorge Portilla
Abstract
The arrival of quantum computers threatens the security guarantees of classical cryptography, since quantum algorithms can break schemes that remain secure against conventional attacks. The National Institute of Standards and Technology (NIST) has therefore standardized a set of post-quantum cryptographic algorithms, among them Falcon, a lattice-based digital signature scheme with the most compact signature and public-key sizes of the standardized candidates. Falcon's reliance on floating-point arithmetic makes it hard to implement in hardware, and prior work offers only partial accelerators for specific operations such as signature generation or verification, or a single full implementation generated through high-level synthesis (HLS). This work presents Peregrino, the first hardware accelerator of the complete Falcon digital signature scheme designed from scratch in HDL, targeting resource-constrained edge devices without a native floating-point unit through an emulated floating-point datapath. Implemented on a single Artix 7 XC7A200T FPGA, Peregrino uses 85261 LUTs, 41382 FFs, 44 BRAMs, and 142 DSPs for the Falcon-1024 variant. Against the only prior full implementation, the HLS-based FalconTakesOff, it uses 1,9$\times$ fewer LUTs, 3,4$\times$ fewer FFs, 2,7$\times$ fewer BRAMs, and 9,9$\times$ fewer DSPs, fitting the entire scheme on one FPGA where the HLS design requires at least two. Operating as a peripheral of an on-chip MicroBlaze soft-core, the accelerator additionally reduces key-pair generation, signature generation, and signature verification clock cycles by 92\%, 96\%, and 85\% over the emulated floating-point reference software.