Multi-asic switches boost network performance with circuit-switched indirection
The Power of Indirection: Scaling Switches Beyond Silicon Boundaries
Networking and Internet Architecture
Summary
Chips used in networks are hitting physical limits, so designs now combine multiple smaller chips (ASICs). But connecting many chips together is tricky because connecting them fully is expensive, and less connection slows down the whole system. The authors created a new design that puts a flexible layer in front of these chips to smartly redirect traffic, cutting down on the hard-to-connect parts and speeding things up. Their system, called Fastroute, mixes packet and circuit switching to keep performance high while saving on connection costs, proven with a hardware prototype running AI training workloads.
What this means in practice
- •For network hardware engineers: Build high-performance multi-ASIC network switches that reduce costly inter-chip bandwidth needs by dynamically remapping traffic paths.
- •For data center infrastructure teams: Deploy switches that support large bandwidth and device counts efficiently for AI training and other high-demand workloads.
Authors
Lukas Röllin, Sushovan Das, Paolo Costa, Laurent Vanbever
Abstract
The slowdown of Moore's law and the area limit of monolithic integration have made chiplet-based designs inevitable across many domains, including network ASICs. However, combining multiple network ASICs together poses a fundamental challenge: maintaining sufficient inter-ASIC bandwidth to match the performance of an idealistic single-ASIC design. Providing full bandwidth is prohibitively expensive as it requires valuable forwarding capacity, while reducing inter-ASIC bandwidth creates severe performance bottlenecks. We propose a novel multi-ASIC switch architecture that introduces a circuit-switched indirection layer in front of the ASICs. This layer flexibly remaps ingress ports across ASICs, localizing traffic and minimizing inter-ASIC communication based on observed patterns. Our system, Fastroute, combines packet and circuit switching to deliver performance comparable to a single-ASIC switch while reducing inter-ASIC bandwidth requirements. This frees up capacity for external network interfaces, allowing Fastroute to outperform traditional non-oversubscribed multi-ASIC designs. Our hardware prototype demonstrates the system's functional feasibility by evaluating it on an LLM training workload. By reducing bandwidth and power overhead, Fastroute bridges the gap between silicon fabrication limits and soaring application demands. It provides an efficient transition to multi-ASIC switches, enabling bandwidth and radix demand to be met without waiting for the next ASIC generation.