Packet iSlip switch improves latency for mixed packet and cell networks
Packet iSlip
Networking and Internet Architecture
Summary
Networks need to send data in small fixed units called cells and larger units called packets, but managing both on the same switch can cause delays. The authors studied a switch design that avoids delays caused by packet queues blocking others, by changing how the switch schedules packets to leave the output. Their improved scheduler, called piSlip, reduces waiting time when reassembling packets, leading to faster data flow without increasing memory needs. Simulations showed piSlip performs better than the original iSlip scheduler for switches handling both cells and packets.
What this means in practice
- •For network hardware engineers: Design packet and cell switches with reduced output latency by using the piSlip scheduler for improved packet reassembly handling.
- •For data center network architects: Implement crossbar switch fabric scheduling techniques to better support mixed cell and packet traffic and reduce packet transmission delays.
Authors
Marc Mosko
Abstract
This paper examines input/output buffered crossbar switches under combined packet and cell data. Our switch architecture uses input buffering with Virtual Output Queues to avoid Head of Line Blocking. The switch fabric is a crossbar with no speedup. We use a modified iSlip [McKeown] crossbar scheduler geared towards packet data, called piSlip. Cell ports are largely unmodified from standard iSlip behavior. For packet output ports, we introduce changes to the grant pointer which minimizes output latency caused by packet reassembly. Our model uses several output states, including packet cut-through. From simulation results, we show that piSlip with virtual cut-through offers latency characteristics significantly better than unmodified iSlip with similar packet port interfaces. Simulation further shows that piSlip and iSlip have similar maximum and average buffering requirements.