Flexible compiler and hardware design speeds up accelerator development
Compiler and Hardware Co-Design for Accelerator Architectures
Hardware Architecture
Summary
Creating specialized computer chips called accelerators can make certain computations much faster, but building both the hardware and software together is usually very complex. The authors developed EAAC, a system that makes it easier to design and test new accelerator hardware alongside the compiler that prepares programs to run on them. Their system focuses on workloads with predictable data patterns and uses MLIR, a tool that supports many programming languages. They showed this approach with an example that speeds up a common math operation by 28 times compared to a basic processor alone.
What this means in practice
- •For hardware accelerator engineers: Build and test new accelerator hardware more quickly by using EAAC’s minimal compiler infrastructure and flexible MLIR integration.
- •For embedded systems developers: Integrate custom acceleration units like systolic arrays with embedded RISC-V cores for faster execution of data-heavy workloads using EAAC’s compilation flow.
Authors
Karl Herman Krause, Emad Jacob Maroun, Martin Schoeberl
Abstract
Heterogeneous accelerator architectures offer an efficient path to performance for compute-intensive workloads. However, full-stack integration remains difficult. We present EAAC (Extensible Accelerator Architecture), a flexible and extensible compiler and hardware architecture designed to lower the overhead of hardware-compiler co-development for rapid prototyping of hardware accelerators. EAAC targets static data-flow workloads with predictable memory access patterns. By using MLIR, we enable possible integration with a range of different frontends that emit MLIR. And by providing a minimal set of compiler functionality that enable necessary data-orchestration we lower the effort needed to get a simple implementation of a hardware acceleration unit up and running, while providing a relatively blank and un-opinionated starting point for further work. We validate this approach with a prototype GEMM accelerator combining a systolic array unit with an embedded RISC-V core, compiled end-to-end through the EAAC MLIR pipeline. On a synthetic fully-connected-layer workload, the accelerator achieves a 28x speedup in execution time over a RISC-V-only baseline, with the GEMM operation itself accounting for only 1.64\% of total execution time. We further characterize the compiler's hardware-semaphore allocation, showing that the number of semaphores required scales linearly with instruction count in the worst case, and identify this as a concrete target for future optimization.