Students develop open source efficient standard cell library for 130nm chips
An Open-Source Standard-Cell Library for IHP 130nm Developed by Students
Hardware Architecture
Summary
Making computer chips often requires building many small components called standard cells. Designing these cells is complex and usually not taught in detail in chip design classes. This paper shows how students at ETH Zurich designed and tested their own open-source set of standard cells using a 130nm technology process. Their student-made library is smaller and more energy-efficient than the existing one, while working just as fast. This new library helps students create entire chips from the basic transistor level.
What this means in practice
- •For digital ic designers: Use the student-developed open-source standard-cell library to reduce area and energy consumption in chip designs at 130nm nodes.
- •For embedded systems engineers: Incorporate the efficient eight-track standard-cell library in custom hardware projects needing energy savings without losing performance.
Authors
Oscar Castañeda, Lavinia Recchioni, Tobias Senti, Flurin Cahenzli, Marco Ferroni, Thorben Heekenjann, Robert Kenter, Stefan Odermatt, Daniel Richner, Gabriel Altendorfer, Davide Cannone, Miguel Correa, Ivan Herger, Lars Kröger, Nicolas Nanzer, Darja Nonaca, Christopher Reinwardt, Lukas Winklhofer, Enrico Zelioli, Yiheng Zhang, Yingxue Zhang, Domenic Keller, Seyed Hadi Mirfarshbafan, Zerun Jiang, Beat Muheim, Arianna Rubino, Jérémy Guichemerre, Frank K. Gürkaynak, Christoph Studer
Abstract
Standard-cell libraries form the critical interface between transistor-level circuit design and automated digital design flows, yet their design and characterization are rarely covered in depth in digital VLSI courses. This paper presents VLSI 5, a graduate-level course at ETH Zurich in which students design, lay out, characterize, and integrate their own standard cells using IHP's open-source 130nm SG13G2 process design kit. In the first course offering, 19 students developed EZ130 8T, an open-source eight-track standard-cell library comprising 220 cells. We evaluate successive library versions using eight synthesis benchmarks, across which EZ130 8T achieves significant area reduction compared to the SG13G2 library at competitive timing. For a postlayout 8x8 matrix-vector multiplier, EZ130 8T reduces cell area by 35% and energy by 39% while maintaining virtually the same clock period. The library has already been adopted in other ETH Zurich VLSI courses, enabling the creation of chips entirely designed by students down to the transistor level.