ChipMEM helps design chips by remembering verified improvements
ChipMEM: Verification-Grounded Memory for EDA Agents
Machine LearningComputation and Language
Summary
Making computer chips requires designing complex circuits that have to work correctly and efficiently. The authors show a method called ChipMEM that helps AI-based chip design tools remember only good ways to improve designs, verified by tests. This memory allows the system to reuse useful fixes on new tasks instead of just repeating trial-and-error on the same problems. They tested ChipMEM on challenging chip design problems and found it made better designs more often and worked well on tasks it hadn’t seen before.
What this means in practice
- •For hardware design teams: Improve chip design tools by enabling them to remember verified successful fixes for reuse across different chip design tasks.
- •For software engineers building ai systems: Incorporate verification-grounded procedural memory and Bayesian ranking to guide AI agents working with complex tools beyond chip design.
Authors
Abdulrahman AlRabah, Joshua Mabry, Dilek Hakkani-Tür, Abdussalam Alawini, Hamid Shojaei, Kartik Hegde, Sandesh Adhikary
Abstract
Large language model (LLM)-based agents use Electronic Design Automation (EDA) tools to generate and revise register-transfer-level (RTL) designs under synthesis and verification feedback. Recent methods learn from this feedback by distilling reusable skills from execution traces or by training on rewards derived from EDA-tools. Both methods are typically evaluated on the tasks that produced the experience. Repeated access to benchmark feedback on the same task can reward task-specific revision rather than creating reusable knowledge that transfers. We introduce ChipMEM, a verification-grounded memory layer for EDA agents. It combines cross-task procedural memory with within-trajectory statistical guidance. Its procedural component distills and stores a skill only after it passes synthesis, simulation, or formal checks, rather than relying on model self-assessments. A Bayesian component maintains hierarchical Beta estimates over tool-call outcomes and ranks recovery strategies that succeeded under comparable errors. A common adapter applies the same memory interface to RTL optimization and testbench-generation agents while preserving each domain's tools and acceptance criteria. We measure performance on training tasks and evaluate whether learned skills transfer to unseen tasks. On RTLRewriter-Bench, under matched model and tool settings, ChipMEM produces equivalence-passing outputs on 39/54 scored designs versus 35/54 without memory; on the 49-design short suite, mean area improvement is 8.69% versus 5.66%. On held-out CVDP tasks, ChipMEM with a frozen procedural library achieves 20/20 accepted outcomes versus 18/20 without memory in a single evaluation per setting.