FPGA accelerator speeds up secure proof computations for scalable blockchain
FASTAR: FRI Accelerator for Scalable Transparent ARguments of Knowledge
Cryptography and Security
Summary
Zero-Knowledge Proofs help prove facts without revealing secrets, but newer secure methods require heavy computations that slow things down. The authors created FASTAR, a special computer chip design using FPGAs to speed up a key step called FRI in these proofs. FASTAR adjusts itself to different devices automatically and uses less power, making these secure proofs more practical. This helps make secure and private computer checks work faster and more efficiently on a wider range of hardware.
What this means in practice
- •For blockchain developers: Build faster, more energy-efficient verifiable computation systems using scalable zero-knowledge proof acceleration on FPGA hardware.
- •For cryptocurrency infrastructure teams: Deploy FPGA-based proof verification accelerators to reduce latency and hardware costs in validating transparent, post-quantum secure transactions.
Authors
Tengkai Gong, Xiaolin Xu
Abstract
Zero-Knowledge Proofs (ZKPs) enable a prover to cryptographically convince a verifier of the validity of a statement without revealing any underlying secrets, forming a foundational primitive for verifiable computation. The ZKP landscape is undergoing a fundamental shift from classic zk-SNARKs such as Groth16, which rely on trusted setup and are vulnerable to quantum adversaries, toward transparent, post-quantum constructions such as zk-STARK. These systems achieve post-quantum security by relying solely on collision-resistant hash functions, however, at the cost of substantial computational overhead. In particular, the Fast Reed--Solomon Interactive Oracle Proof of Proximity (FRI) protocol dominates prover complexity, generating massive data volumes, repeated Merkle-tree commitments, and irregular memory access patterns that limit performance and energy efficiency on general-purpose processors. To address these challenges, this work proposes FASTAR, a novel FPGA-based accelerator for the FRI protocol. Unlike accelerators that pursue fixed high-performance kernels on expensive ASIC process nodes, FASTAR adopts a constraint-driven design methodology. Our framework is implemented with High-Level Synthesis (HLS) and composed of fully parameterizable building blocks for the major stages of FRI, including polynomial evaluation, recursive split-and-fold, and Merkle-tree construction. From user-provided board specifications, FASTAR automatically generates hardware implementations tailored to the resource and memory constraints of the target FPGA, enabling deployment across a wide range of platforms without manual redesign.