NPU accelerator enables real-time vehicle detection on PYNQ-Z1 FPGA board
NPU Accelerator: Quantized Real-Time Vehicle Detection on PYNQ-Z1 Using FINN
Hardware ArchitectureArtificial Intelligence
Summary
Detecting vehicles quickly and efficiently on small, limited devices is challenging. The authors built a special hardware accelerator on a PYNQ-Z1 board that can find vehicles in video at over 30 frames per second while using low power. They combined smart neural network simplifications, low-precision calculations, and hardware optimization to meet speed, power, and accuracy goals. Their system runs a smaller version of YOLO, a popular detection model, and achieves good vehicle detection performance within strict time and energy limits.
What this means in practice
- •For embedded system engineers: Integrate real-time, energy-efficient vehicle detection on resource-limited FPGA platforms using quantized YOLO models.
- •For automotive electronics developers: Develop low-power vehicle detection hardware for driver assistance or traffic monitoring leveraging FPGA-based NPU acceleration.
Authors
Daniel Gutierrez, Antonio Cuesta, Jorge Fe, Bruno Gutierrez, Rashed Al Koutayni
Abstract
This paper presents the design, optimization, implementation, and on-board validation of a neural processing unit (NPU) accelerator for real-time vehicle detection on the resource-constrained Xilinx Zynq XC7Z020 device of the PYNQ-Z1 board. The work follows a hardware/software co-design methodology that combines quantization-aware training (QAT), lightweight YOLO-derived detectors, Brevitas/QONNX model export, FINN dataflow compilation, Vivado implementation, and physical benchmarking on the target board. Four simultaneous engineering requirements define successful deployment: throughput above 30 frames/s (FPS), energy efficiency above 7 FPS/W, programmable-logic (PL) hardware latency below 50 ms, and Pascal VOC detection accuracy above 0.55 mAP@0.5. The design space includes LP-YOLO and LP-YOLO Slim variants, a custom YOLOv3-tiny reference, 4-bit and mixed low-bit quantization, 320$\times$320 and 256$\times$256 inputs, manual and automatic FIFO sizing, and programmable-logic clocks from 100 to 200 MHz. The final LP-YOLO Slim configuration uses a 256$\times$256 input, w2a4 quantization, and a 142.86 MHz PL clock. With batch 100 it reaches 35.66 FPS at 2.91 W, corresponding to 12.25 FPS/W, while measured PL latency is 45.11 ms and VOC mAP@0.5 is 0.594. This is the only evaluated configuration for which the supplied measurements satisfy all four requirements simultaneously. The results show that low-bit QAT, architectural slimming, FINN folding and FIFO optimization, and moderate clock scaling can jointly provide a practical real-time detector on a small Zynq FPGA.