Agentic chip design improves speed with higher-level abstractions
Can Agents Design Better Chips with a Higher Level Abstraction?
Artificial IntelligenceHardware Architecture
Summary
Designing computer chips is complicated, and new AI tools called agents are being used to help. Most agents try to design chips at a very detailed level, but this paper finds they can do better when working with higher-level designs first. The authors show that a combined approach, starting with a high-level design and then refining it at a lower level, runs chips faster. They tested this on many tasks and saw big improvements over traditional methods.
What this means in practice
- •For chip design engineers: Speed up chip development by combining high-level synthesis and RTL refinement with AI agents to produce more efficient designs.
- •For hardware acceleration teams: Use AI-assisted workflows to create faster FPGA implementations by exploiting design abstractions and agent refinements.
Authors
Zijian Ding, Yang Zou, Yizhou Sun, Jason Cong
Abstract
Large Language Model (LLM) agents are increasingly being explored for chip design, but most existing approaches operate directly at RTL. We ask whether agents can design better chips by leveraging higher-level abstractions. We compare Direct RTL Design, Agent-based HLS Design, Post-Compiler HLS Refinement, and Post-HLS RTL Refinement, and combine Agent-based HLS Design with Post-HLS RTL Refinement as Agent-based HLS with RTL Refinement (AHRR). We use FPGAs as a practical, easy-to-deploy platform for end-to-end evaluation, but note that the design-flow tradeoffs we study are largely independent of the target technology. Across a diverse 11-tasks benchmark suite, AHRR achieves a 2.6$\times$ geometric-mean speedup over Direct RTL Design across our benchmark suite. Case studies show that HLS distills design knowledge into abstractions that agents can leverage, while RTL refinement recovers lower-level optimization opportunities. Together, these results make AHRR a promising workflow for agentic chip design. The code and evaluation artifacts are available at https://github.com/ZijD/AHRR.