Positive feedback adiabatic logic shows energy benefits in 16nm FinFET circuits
Evaluating Positive Feedback Adiabatic Logic in 16nm FinFET with a Realistic Power-Clock
Hardware Architecture
Summary
Computers use energy whenever they switch electrical signals, and adiabatic logic is a technique that recycles some of that energy to save power. The authors tested a type of adiabatic logic called PFAL in a realistic modern chip process and found it can use up to five times less energy than traditional chip designs at lower speeds. They identified sources of energy loss unique to this method and showed their design works well even with a practical power supply. This suggests PFAL could help build more energy-efficient chips in the future.
What this means in practice
- •For low-power chip designers: Design energy-efficient digital circuits by integrating PFAL logic for improved energy-delay trade-offs in 16nm FinFET technology.
- •For hardware verification engineers: Use the detailed PFAL evaluation data and power-clock model to simulate and verify low-power circuit functionality under realistic conditions.
Authors
Franciszek Łukowski, Maciej Pyrzowski, Aida Todri-Sanial
Abstract
Adiabatic logic reuses the energy stored on load capacitances through quasi-reversible switching, enabling a lower minimum energy consumption than conventional static CMOS. Yet its practicality in FinFET technologies and at multi-GHz clock rates has yet to be investigated. This work provides a systematic evaluation of Positive Feedback Adiabatic Logic (PFAL) simulated in the TSMC 16nm FinFET process. A set of PFAL standard-cell gates were realised, along with two representative combinational circuits - a 2$\times$2 multiplier and a 4-bit comparator - and compared against static CMOS logic using the energy--delay product (EDP) and the energy advantage metric $η= E_{\mathrm{CMOS}} / E_{\mathrm{PFAL}}$. Transient simulations reveal three sources of non-adiabatic loss: two specific to the PMOS/NMOS latch, threshold-voltage-related loss and a previously unreported redundant charging of the output node and one related to the complexity of PFAL logic trees. The low-threshold Buffer/NOT cell achieves a minimum EDP of $1.23\times10^{-26}$J$\cdot$s at $V_{\mathrm{CLK}} = 0.6$V and $f_{\mathrm{CLK}} = 7.94$GHz, while PFAL preserves an energy benefit over static CMOS of up to roughly $5\times$ at reduced frequencies and elevated supply voltages. A parallel-coupled quadrature voltage-controlled oscillator is designed as a realistic four-phase power-clock generator. With this non-ideal supply, the Buffer/NOT energy stays within $2\%$ of the ideal sinusoidal case at $3$GHz. A loading study quantifies the phase shift and amplitude reduction induced by increasing fan-out. Overall, the results provide a design-oriented evaluation of PFAL in 16nm FinFET and a motivation to exploit adiabatic logic for future low-power system architectures.