Splyce boosts sparse tensor processing by removing control flow bottlenecks
Splyce: SIMD Vectorization of Sparse Coiteration
Programming LanguagesHardware ArchitecturePerformance
Summary
Sparse tensor operations are important but slow because they involve complex loops that are hard for computers to speed up. The authors created Splyce, a new way for compilers to turn these tricky loops into simpler code without unpredictable branches, letting the computer do many steps at once more efficiently. This approach made common sparse tensor tasks run nearly twice to almost three times faster in tests. Splyce works by translating irregular data patterns into a steady flow, so modern processors can handle them better.
What this means in practice
- •For machine learning engineers: Accelerate sparse tensor operations in ML models to speed up training and inference on irregular data.
- •For high-performance computing developers: Optimize scientific simulations that use sparse data structures for faster execution on modern CPUs.
Authors
Kabilan Mahathevan, Poorna Gunathilaka, Kirshanthan Sundararajah
Abstract
Sparse tensor contractions are bottlenecked by sparse-sparse coiteration loops that resist standard loop vectorization. We present Splyce, an auto-vectorization framework in MLIR that overcomes this through a dual-path execution model. By decoupling coordinate intersection from pointer management via selective predication, Splyce inherently eliminates data-dependent branches as a side effect, allowing modern superscalar engines to maximize instruction-level parallelism and hide memory latency. Beyond simple branch elimination, our transformation exposes independent computation that can be executed concurrently, increasing functional-unit utilization that would otherwise be constrained by sequential dependencies. Evaluation across foundational sparse tensor kernels demonstrates performance ranging from 1.96X to 2.86X on synthetic inputs, with consistent speedups sustained across a vast majority of irregular real-world datasets from the SuiteSparse collection. Ultimately, Splyce demonstrates that by converting unpredictable control-flow into a predictable data stream, compiler-driven speculation can effectively reconcile the memory efficiency of compressed storage with the execution-unit throughput of modern superscalar architectures.