Framework improves hardware speed and size for elliptic curve operations
Locus: A Framework for Exploring and Optimizing Point Addition Hardware for Zero-Knowledge Proofs
Hardware ArchitectureCryptography and Security
Summary
Zero-Knowledge Proofs help keep information private and verify computations but require complicated math that is slow to compute. One key math step is called point addition on elliptic curves, which prior hardware designs only handled for a few types and setups. The authors created Locus, a tool that automatically builds and tests hardware designs for many different elliptic curves to find faster and smaller options. Their designs speed up computations by over 2.7 times and reduce chip size by over 3 times compared to previous hardware, also improving end-to-end proof speeds significantly.
What this means in practice
- •For cryptographic hardware engineers: Build optimized point addition units for various elliptic curves in ASICs and FPGAs to improve ZKP hardware performance and reduce chip area.
- •For blockchain developers: Integrate faster elliptic curve operations into zero-knowledge proof accelerators to speed up transaction verification and maintain privacy.
Authors
Gaurav Kuwar, Alhad Daftardar, Jianqiao Mo, Siddharth Garg, Brandon Reagen
Abstract
Zero-Knowledge Proofs (ZKPs) are critical for privacy-preserving and verifiable computation, but their cryptographic primitives impose high computational overheads. One such primitive is point addition (PADD) on elliptic curves. Several prior works have implemented PADDs in hardware, but only for a few specific elliptic curves and design points, leaving a large design space unexplored, and lacking systematic guidance on hardware design trade-offs. To address this gap, we present Locus, a framework dedicated to optimizing and exploring point addition hardware. Given the parameters of any elliptic curve in a supported equation form, Locus automatically generates ASIC and FPGA implementations of PADD, enabling systematic exploration of the PADD design space. Using Locus, we conduct the first comprehensive hardware-focused study of PADD designs, exploring trade-offs over 1,000 design points. On a 12nm technology node, our framework produces PADD designs that yield a $2.71\times$ geomean speedup and $3.11\times$ geomean area reduction compared to prior ASICs, $34.67\times$ geomean speedup over CPU, and $3.15\times$ geomean speedup on end-to-end proof generation when integrated into a prior ZKP accelerator at iso-area. Locus is available at https://github.com/cryptolets/cryptolets/tree/locus.