FPGA platform speeds up approximate multipliers evaluation for dnn retraining
FAME: An FPGA-Based Platform for Approximate Multipliers Evaluation with Pattern-Guided DNN Retraining
Hardware ArchitectureMachine LearningPerformance
Summary
Approximate multipliers help reduce energy and hardware needs for deep learning models but cause some errors. Evaluating many such multipliers on big datasets is slow when done on CPUs or GPUs using software tricks. The authors built FAME, a system that runs approximate multipliers directly on special reprogrammable chips called FPGAs, making evaluation much faster. They also created a way to retrain models guided by multiplier error patterns to regain lost accuracy. Their tests show large speed improvements and better accuracy recovery compared to older methods.
What this means in practice
- •For hardware design teams: Evaluate and optimize approximate multipliers within DNN hardware accelerators more efficiently using direct FPGA implementation.
- •For machine learning engineers: Improve DNN inference accuracy by retraining models guided specifically by the error patterns of deployed approximate multipliers.
Authors
Rappy Saha, Nima Amirafshar, Jude Haris, Nima Taherinejad, José Cano
Abstract
Approximate multipliers can reduce hardware area and energy consumption in Deep Neural Network (DNN) inference; however, they introduce computational errors. Assessing the accuracy of numerous approximate multiplier designs across diverse DNN models and large-scale datasets remains challenging due to prohibitive evaluation times. This overhead primarily stems from the slow emulation of approximate multiplier behavior using look-up tables (LUTs) on CPU and GPU platforms. Moreover, the resulting accuracy degradation must be carefully quantified and, if necessary, mitigated (e.g., through retraining), further increasing the overall evaluation cost. To address these challenges, we propose FAME, an FPGA-based platform for evaluating approximate multipliers. The platform exploits the reconfigurable logic of Field-Programmable Gate Arrays (FPGAs) to implement approximate multipliers directly in hardware, eliminating the need for LUT-based emulation on CPU/GPU platforms and thereby enabling efficient DNN inference while significantly reducing evaluation time on large datasets. Furthermore, we introduce a pattern-guided DNN retraining technique to mitigate accuracy degradation induced by approximate multipliers. Specifically, retraining is guided by multiplier-specific patterns to effectively recover potential accuracy losses. We evaluate FAME using two DNN models, ResNet-18 and MobileNetV2, on the ImageNet dataset across 27 approximate multipliers. During inference, our approach achieves up to a 3.47x speedup in approximate multiplier evaluation compared to prior LUT-based emulation methods. Furthermore, the proposed retraining technique improves accuracy by up to 65.5% over existing retraining approaches for the evaluated multipliers. The code is publicly available at: https://github.com/gicLAB/FAME