Spectral graph reuse speeds vision graph neural networks on FPGAs
SpecReuse: Spectral Graph Reuse for Efficient Vision GNN Inference on FPGAs
Distributed, Parallel, and Cluster Computing
Summary
Vision graph neural networks use graphs to understand images, but rebuilding these graphs at every step slows down and drains energy from specialized chips called FPGAs. The authors created a new method called SpecReuse that checks whether the graph needs to be rebuilt by looking at a small summary of the data instead of always doing the full reconstruction. This makes the process up to 2.7 times faster and saves more than half the energy, with almost no impact on how well the network recognizes images. They also built hardware that supports this approach on FPGAs without needing much extra space.
What this means in practice
- •For fpga hardware engineers: Design FPGA accelerators for vision GNNs with lower latency and energy by exploiting spectral graph reuse.
- •For embedded systems developers: Integrate efficient vision GNN inference into edge devices by reducing graph construction overhead on specialized hardware.
Authors
Isabella Bernhardt Eiliya, Anvitha Ramachandran, Dhruv Parikh, Viktor Prasanna
Abstract
Dynamic Image Graph Construction (DIGC) is the primary performance bottleneck in FPGA acceleration of Vision Graph Neural Networks (ViGs), reconstructing graph connectivity at every layer through irregular, memory-intensive computation. Existing FPGA accelerators optimize DIGC but still execute it unconditionally, making repeated graph reconstruction a persistent source of latency and energy consumption. We propose the SpecReuse algorithm, which computes compact spectral descriptors of intermediate features and reuses previously constructed graphs when descriptor drift remains below a calibrated threshold. We further present the SpecReuse accelerator, an FPGA architecture that realizes graph reuse through lightweight hardware for spectral descriptor extraction and reuse control while remaining compatible with existing graph-construction accelerators. Experimental results demonstrate up to a $2.69\times$ speedup in end-to-end inference and approximately 58--65\% lower energy per inference with negligible FPGA resource overhead and minimal loss in classification accuracy.