Llm framework boosts Verilog generation accuracy using spec-driven constraints
SpecLens: LLM-Based Verilog Generation with Specification-Derived Constraints via Behavioral Divergence
Hardware Architecture
Summary
Creating Verilog code, used to design computer chips, directly from written instructions is very hard. The authors developed SpecLens, a method that makes large language models (LLMs) generate better Verilog using checks based on the original instructions instead of guesswork. SpecLens compares several generated versions to find differences and uses these to tighten the constraints, leading to more accurate and faithful hardware designs. It achieved higher correctness rates than previous methods and did not need repeated fixing cycles.
What this means in practice
- •For hardware design engineers: Generate RTL code from natural-language specs with higher functional accuracy and specification adherence.
- •For verification teams: Use SpecLens to reduce reliance on trial-and-error compile-repair loops during hardware description generation.
Authors
Wen Bing, Bing Li
Abstract
Large language models (LLMs) have recently shown promise in Verilog generation, but producing functionally correct RTL directly from natural-language specifications remains a highly challenging task. Existing approaches improve LLM-based Verilog generation mainly with retrieval-augmented generation (RAG), self-planning, or few-shot prompting. However, these methods focus primarily on external or generic forms of enhancement rather than strengthening the specification with task-specific constraints. In this work, we propose SpecLens, an automated framework for LLM-based Verilog generation that derives specification-driven constraints by analyzing behavioral divergence among multiple candidate implementations, using the original specification as the only external semantic source during generation. On the VerilogEval v2.0 spec-to-RTL benchmark, SpecLens achieves a functional pass@1 ratio of 86.2\% with o3-mini-medium and 89.4\% with o3-mini-high. This corresponds to a 3.6 percentage-point gain over the SOTA prompting method with o3-mini-medium and a 3.8 percentage-point gain over the SOTA behavioral divergence method with o3-mini-high. In addition, on RTLLM v1.1 and v2.0, analysis shows that SpecLens is more specification-faithful and less prone to benchmark-aligned priors. SpecLens achieves 100\% syntactic correctness on VerilogEval v2.0, 86.2\% on RTLLM v1.1, and 88\% on RTLLM v2.0, even without using costly compile-repair loops to revise generated code iteratively. The code is open source and available at https://anonymous.4open.science/r/SpecLens-4632/readme.md.