FPGA optimization improves jet classification accuracy and speed
FINNAS: FINN-Guided Hardware-Aware NAS and Pruning for FPGA Jet Substructure Classification
Hardware Architecture
Summary
FPGAs are special computer chips that can run small neural networks very fast and with low power. The authors created FINNAS, a tool that automatically finds good neural network designs tailored to these chips, saving the time of manual tweaking. FINNAS tries different network sizes and precision levels, predicts their performance and chip usage, then picks the best ones to fully test and prune. Using FINNAS on a particle physics task, they found designs that are more accurate and use much fewer chip resources than a previous expert design.
What this means in practice
- •For fpga hardware designers: Automatically find compact neural networks with better accuracy and lower resource usage for FPGA accelerators in real-time classification tasks.
- •For high energy physicists: Deploy improved neural network models efficiently on FPGA-based detectors for analyzing jet substructure in particle collisions.
Tested on one dataset.
Authors
Eva Chauffour, Changhong Li, Georgios Floros, Shreejith Shanker
Abstract
FPGAs are well suited to deploying quantised neural networks (QNNs) under strict accuracy, latency, and resource constraints; however, identifying efficient model-accelerator combinations commonly requires extensive manual design-space exploration and repeated hardware synthesis. This paper presents FINNAS, a FINN-guided hardware-aware evolutionary neural architecture search framework. FINNAS jointly searches quantised MLP depth, width, and global precision settings, and ranks candidates using proxy validation accuracy together with FINN-estimated LUT usage and latency under a fully parallel mapping. Selected finalists are fully retrained, subjected to post-search unstructured pruning, and validated using RTL simulation and Vivado out-of-context synthesis. On the CERNBox jet substructure classification task, the searched implementations expose competitive accuracy-resource trade-offs. Compared with a manually optimised dense FINN accelerator, a compact FINNAS design improves accuracy from 73.78\% to 74.36\%, while reducing LUT usage by \(8.5\times\) and RTL-simulation latency by \(1.77\times\). Unstructured pruning further provides consistent LUT and FF reductions across the fully parallel finalists.