Multimodal model improves circuit schematic understanding using topological reasoning
Circuit-MLLM: Topological Logic-Guided Latent-Space Visual Reasoning for Circuit Schematic Understanding
Computer Vision and Pattern RecognitionArtificial IntelligenceMachine Learning
Summary
Circuit diagrams are complicated because parts are packed closely together and connected in specific ways, which makes them hard for usual AI models to understand. The authors created Circuit-MLLM, a system that looks at circuit diagrams by finding parts, tracing connections, and reasoning through these steps using a kind of hidden language inside the model. Their approach helps the system grasp the wiring and layout better than before, beating other strong AI models. This means it can better read and analyze circuit designs automatically.
What this means in practice
- •For electronic design automation engineers: Automatically extract and analyze circuit topology from schematics to accelerate electronic design workflows.
- •For printed circuit board manufacturers: Improve automatic verification and error detection by understanding detailed circuit connections from schematic images.
Authors
Jinyuan Deng, Yuqi Jiang, Wenjing Huang, Xin Li, Qi Sun, Cheng Zhuo
Abstract
Through pre-training on extensive text and image datasets, current multi-modal large language models (MLLMs) achieve strong performance on general tasks. However, circuit schematics present a unique challenge for MLLMs due to their dense component layouts and distinct topological logic, demanding fine-grained structural parsing to extract the electrical semantics. To address this, we propose Circuit-MLLM, a multimodal reasoning framework that reformulates circuit topology analysis as a process of device localization, path tracing, and sequential reasoning within the latent space. We introduce a circuit knowledge mining mechanism that deeply aligns the model's latent representations with structurally rich features derived from multi-granularity circuit vision experts, enabling the model to effectively internalize topological semantics. Building upon these internalized semantics, we devise a topology-guided sequencing strategy that decouples reasoning from the rigid raster-scan order, enforcing stepwise inference along the circuit's topological logic in latent space. Across diverse circuit analysis tasks, Circuit-MLLM consistently outperforms strong baselines, notably achieving a 25% higher average score than GPT-5.1, which demonstrates the effectiveness of our framework in circuit schematic topology analysis. Code is publicly available at https://github.com/IC-Yuan/Circuit-MLLM.