Scalability challenges limit fault-tolerant trapped-ion quantum computers
WISER: Systematic Design-Space Exploration of Fault-Tolerant Global Control Trapped-Ions
Hardware Architecture
Summary
Scaling up trapped-ion quantum computers faces major challenges with wiring and power, which can slow down error correction needed for reliable operation. The authors created WISER, a tool to explore how new wiring-reducing designs called WISE affect performance and error rates. They found only a small range of designs that might work well, but even those run noticeably slower than traditional setups. This trade-off means making these systems practical will require big improvements in error rates and circuit efficiency.
What this means in practice
- •For quantum hardware engineers: Design scalable trapped-ion quantum processors by evaluating hardware-control trade-offs for reliable quantum error correction with minimal wiring complexity.
- •For quantum compiler developers: Optimize compilers to target globally controlled trapped-ion systems using WISE architectures to achieve feasible fault-tolerant workloads.
Authors
Scott Jones, Song-qing-hao Yang, Prakash Murali
Abstract
Trapped-ion quantum computers are a leading candidate for scalable fault-tolerant quantum computing, but conventional Quantum Charge-Coupled Device (QCCD) architectures face severe wiring and power constraints as systems scale. The recently proposed WISE promise orders-of-magnitude reductions in wiring complexity but fundamentally alter the hardware--software interface, making it unclear whether such restrictive architectures can feasibly execute quantum error correction (QEC) and eventually support fault-tolerant workloads. We present WISER, a cross-layer architectural design-space exploration framework for globally controlled trapped-ion systems, to determine whether WISE can support early FTQC, and what hardware/compiler/QEC choices are needed. WISER combines novel WISE-specific compilation, noise modelling, and simulation and integrated them into a unified framework. WISER provides comparative lower-bound estimates of logical clock speed and logical error rate, rather than absolute hardware prediction, enabling us to identify viable operating regions while ruling out infeasible ones. To our knowledge, it is the first systematic design space exploration study targeted at WISE and scalable architectures beyond QCCD. Using WISER, we identify a narrow feasible design space requiring two-ion traps, moderate control multiplexing, aggressive recooling, and high-rate bivariate-bicycle codes. Even under $\sim 10\times$ improvements in physical errors, the lower-bound cycle time to achieve $< 10^{-8}$ logical error is $\approx 100\,ms$, which is $3\times$ slower than local control. These results expose a fundamental trade-off between wiring scalability and logical throughput, suggesting that practical early fault-tolerant operation requires complementary $> 10\times$ physical error rate reductions along with substantial $> 100\times$ reduction in fault-tolerant circuit-depth.