AccelForge streamlines AI accelerator design and evaluation significantly
AccelForge: Comprehensive Modeling and Co-Design Framework for AI Accelerators
Hardware Architecture
Summary
Deep learning tasks use a lot of energy and need special hardware called accelerators to run efficiently. The researchers created AccelForge, a tool that helps designers quickly test and improve these hardware designs. It does this by combining many technical parts like devices, circuits, architectures, and software mapping into one easy-to-use system. This makes it much faster and simpler to explore new ideas and find better ways to run AI workloads. AccelForge is also designed in Python, which helps researchers quickly adjust and build on it.
AI acceleratordeep neural networkstensor algebraworkload mappinghardware modelingenergy efficiencyarchitecture designcircuit modelingPython programmingperformance evaluation
Authors
Tanner Andrulis, Michael Gilbert, Vivienne Sze, Joel S. Emer
Abstract
Tensor algebra workloads, of which deep neural networks are prominent examples, are energy-intensive workloads in modern datacenter and edge deployments, making accelerators necessary to achieve energy efficiency and high throughput. To quickly evaluate and iterate on accelerator designs, we need an accelerator modeling framework that captures salient attributes of devices, circuits, architectures, workloads, as well as optimizing the mapping of the workload onto the hardware. In this paper, we introduce AccelForge, which improves upon existing accelerator modeling frameworks in capabilities, speed, and ease-of-use. AccelForge unifies and multiple works into one framework, and it includes (1) composable user-defined and user-modifiable models of devices, circuits, and architectures, (2) fast mappers that enable accurate evaluation in orders of magnitude less (computer and human) time, and (3) easy-to-use and easy-to-extend, yet still high performance, Python implementations of both the model and mapper to enable rapid research and extension to novel optimizations.