Time based readout improves energy efficiency of analog neural networks
A Time-Based Readout for Vector-Matrix Multiplication in Fully Analog Memristive SNNs
Emerging TechnologiesArtificial IntelligenceHardware Architecture
Summary
Artificial neural networks rely on math operations called vector-matrix multiplications, which are usually slow and power-hungry because of moving data around. The authors focus on spiking neural networks that compute these operations inside memory using special devices called memristors, but traditional ways of reading the results waste space and energy. They propose a new way that converts voltage into time signals to read results more efficiently without complex circuits. Their tests show this method works well for digit recognition tasks and can save space and power.
What this means in practice
- •For embedded system designers: Build low-power, compact spiking neural network processors for real-time tasks like digit classification using time-based readout from memristive arrays.
- •For neuromorphic hardware developers: Improve area and energy efficiency of analog memristive neural network chips by adopting voltage-to-time output conversion.
Authors
Elia Mateu-Barriendos, Álvaro Gómez-Pau, Josep Rius, Daniel Arumí, Rosa Rodríguez-Montañés, Salvador Manich
Abstract
Artificial neural networks rely on vector-matrix multiplications (VMMs), whose implementation in von Neumann architectures is dominated by costly data movement between memory and processing units. Spiking neural networks (SNNs) mitigate this bottleneck by performing in-memory, analog VMMs using memristive crossbar arrays. However, conventional current-mode readout circuits incur significant area and power overhead. This work proposes a fully analog readout architecture based on voltage-to-time conversion of the VMM output. By sensing the column voltage, the proposed approach avoids current-mode summing and scaling circuitry, improving area and energy efficiency. Post-layout simulations of a 10x1 SNN implemented in a 130 nm CMOS technology validate the proposed architecture, while application to a trained 64x10 SNN for digit classification further demonstrates its feasibility for SNN inference.