Neuromorphic hardware explores true power-law memory scaling limits
Fractional-order hardware for neuromorphic computing: Is the order really the problem?
Emerging TechnologiesNeural and Evolutionary Computing
Summary
Neuromorphic systems mimic brain functions by handling signals over many timescales, which is tricky with traditional circuits. The authors investigate special fractional-order circuits that use one setting to cover many timescales but require managing growing memory for past signals. They analyze hardware designs, showing that the practical limits hinge on how long past data is stored and precision limits in representing numbers. They conclude the main challenge is not the fractional order parameter itself but covering low-frequency signal ranges with suitable devices.
What this means in practice
- •For embedded hardware developers: Design neuromorphic chips balancing memory cost and precision limits for long-timescale signal processing.
- •For analog circuit designers: Build fractional-order elements targeting low-frequency signal bands underserved by existing discrete devices.
A survey. It maps existing work.
Authors
Christof Teuscher
Abstract
Does a neuromorphic system need a true power-law memory kernel, and if so, can anyone build one? Neuromorphic systems process signals spanning many timescales at once, from milliseconds to tens of seconds. Integer-order circuits buy each additional timescale with an additional state variable. Fractional-order dynamics offer a different bargain: one operator whose power-law kernel carries a continuum of timescales, tuned by one parameter, the order alpha. A fractional derivative is non-local, so evaluating it costs storage and arithmetic that grow with the retained history, where an integer-order derivative costs a constant. This review organizes the hardware literature around that cost. We derive the retained history needed to hold the truncation error below a tolerance epsilon, show that it scales as epsilon^(-1/alpha), and set beside it a second and independent limit on the direct form: in fixed point the weights themselves underflow, so word length caps the usable history however long the buffer is. The two limits move at very different rates with the order, and where they cross decides whether a word length can serve an order at all. We use both to sort published hardware into three strategies, note a fourth the numerical literature has developed and this hardware has not, and survey digital, analog and device work. Along the way we ask whether the field is worried about the right obstacle. It is not. Fabricated constant-phase devices already span the orders two groups identify as task-optimal, so the order gap has largely closed, leaving a residual gap near 0.1 and at the lower order describing cortical adaptation. What remains is a frequency-band gap of about three decades at the low end. That corner is not empty, since double-layer electrodes work there, but every device in it is discrete, and no integrable thin-film element has been characterized there.