Scheduling quantum tasks on multiple devices to reduce errors
Fidelity-Aware Scheduling of Quantum Circuits on Multi-QPU Systems
Artificial IntelligenceEmerging Technologies
Summary
Quantum computers are very sensitive to errors that build up when running programs, especially on noisy current devices. The authors developed a method to predict how likely a quantum program will run accurately on each available quantum processor before actually running it. Using these predictions, their scheduler assigns tasks to different quantum processors to balance speed and accuracy. This approach helps save time and computing resources compared to testing every possibility.
What this means in practice
- •For quantum computing engineers: Assign quantum programs to suitable processors by estimating expected accuracy without full compilation on every device.
- •For high performance computing teams: Run multiple quantum circuits in parallel across different processors while controlling the trade-off between speed and result accuracy.
Authors
Innocenzo Fulginiti, Antonio Tudisco, Salvatore Zammuto, Patrick Hopf, Deborah Volpe, Helmut Seidl, Giovanna Turvani, Robert Wille, Christian B. Mendl, Martin Schulz
Abstract
High Performance Computing-Quantum Computing (HPCQC) platforms expose multiple Quantum Processing Units (QPUs) that may differ in size, topology, native gates, and noise characteristics. For current noisy devices, errors compound along the compiled circuits quickly, and minimizing them, that is, maximizing the circuits' execution fidelity, is essential for reliable results. Fidelity depends on the compilation to a specific target device: the same high-level circuit may produce different executables and, therefore, different expected fidelities across QPUs. We present a low-overhead fidelity-aware scheduling framework for multi-QPU systems based on a Graph Neural Network (GNN) that estimates, before compilation, the expected fidelity of each circuit on each available QPU. Then, a tunable scheduler uses these estimates to control the trade-off between execution fidelity and parallelism. Results show that this framework allows for approximating an exhaustive fidelity-based assignment, saving computational resources compared to a brute-force approach that compiles each circuit on every device.