Chip solves large complex optimization problems with less power
Differential Stochastic Simulated Annealing Processor for Fully Connected 2048-Spin Optimization
Hardware Architecture
Summary
Finding the best solutions to complex problems with thousands of parts can take a lot of time and energy. The authors designed a special computer chip that simulates a process called annealing to efficiently solve these problems using 2,048 connected parts. Their design saves power and works faster than previous similar chips. This approach could help make solving big optimization problems quicker and more energy-efficient.
What this means in practice
- •For embedded systems engineers: Develop hardware accelerators for solving large-scale optimization problems more efficiently in embedded devices using the proposed annealing processor design.
- •For operations research teams: Use the chip architecture to speed up complex decision-making problems involving many interconnected variables such as scheduling or network design.
Authors
Naoya Onizawa, Md Mohaimenul Alam, Sean Smithson, Duckgyu Shin, Takahiro Hanyu
Abstract
A 2,048-spin fully connected annealing processor based on differential stochastic simulated annealing (DSSA) is presented as an architectural design in TSMC 28 nm CMOS with a 3 mm x 4 mm post-layout area. The processor closes timing at 500 MHz, integrates a 16 Mb SRAM weight memory, and amortizes stochastic noise across 16 spins with area-efficient random number generators. DSSA keeps a serialized datapath for density but recomputes interactions only for spins that flip, shrinking the effective workload to the active frontier during each annealing run. Spin-select scheduling, priority-based weight reads, and a temperature controller that skips idle steps accelerate sparse updates without sacrificing full connectivity. Post-layout simulation results show 2.7 ms time-to-solution (TTS) and 0.86 mJ energy-to- solution on 2,000-spin problems at 316 mW (0.15 mW/spin), achieving 1.5x lower power and 3.5x lower TTS energy than projected prior fully connected annealers. These results demonstrate the potential of the proposed DSSA architecture for large-scale combinatorial optimization hardware under post-layout evaluation.