Digital chip with 27,648 spins solves complex problems fast
A 28nm 27,648-Spin Multichip Digital Ising Accelerator with Pegasus Connectivity
Hardware ArchitectureEmerging Technologies
Summary
Solving some kinds of problems can be very hard even for powerful computers. The paper describes a digital chip design that simulates a system called an Ising model with 27,648 spins spread over four connected chips. This system updates very quickly and can handle complex connections between spins, allowing it to solve big optimization problems in just microseconds. The authors show an example solving a large MaxCut problem efficiently using this setup.
What this means in practice
- •For hardware engineers: Use the described multichip Ising accelerator architecture to build digital hardware specialized for high-speed combinatorial optimization tasks.
- •For quantum-inspired algorithm developers: Integrate programmable Ising couplings with Pegasus connectivity to implement and test efficient probabilistic logic and optimization algorithms in hardware.
Authors
Tong Wu, Atharva Raut, Ian Khor, Ziyad Alswaidan, Ting-Yu Lee, Hongchang Kuang, Navid Anjum Aadit, Anand Raju, Dhruv Chinmay, Siddharth Das, Ken Mai, Kerem Camsari, Tathagata Srimani
Abstract
We present a 28nm digital Ising accelerator with 27,648 spins across four chips. A time-multiplexed spin-update array with local SRAM and scheduled interchip transfers delivers 41.5G updates/s at 1.2pJ/update. Degree-15 Pegasus connectivity and 10b coefficients increase native connectivity and precision over degree-8, 5b multichip annealers. Programmable couplings support optimization and probabilistic logic, with a four-chip planted-MaxCut trace reaching the solution for 27,069 nodes in 3.3$μ$s.