Non-uniform Memory Partitioning For Low-Power Spiking Neural Networks
2026-08-31 • Hardware Architecture
Hardware Architecture
AI summaryⓘ
The authors address the high power use in Spiking Neural Networks caused by frequent memory access to synaptic weights. They propose a system that stores frequently used weights in fast, shallow memory banks and less-used weights in slower, deeper banks to save energy without increasing chip size much. Using automatic design exploration, their method cuts memory access power by up to 61% and uses less area than traditional uniform memory designs. This approach optimizes memory based on how often neurons fire, reducing overall power consumption efficiently.
Spiking Neural Networkssynaptic weightsSRAMmemory banksfiring ratepower consumption28-nm CMOSmemory architectureautomatic design exploration
Authors
Simon Richter, Darío Fernández Khatiboun, Maryam Sadeghi, Milad Zamani, Farshad Moradi
Abstract
Spiking Neural Networks (SNNs) naturally excel in processing temporally rich and sparse data. However, because of their time-stepped processing, memory access, specifically to synaptic weights stored in SRAM (static random-access memory), tends to dominate total power consumption. To address this issue, without incurring a large area overhead, we propose to leverage the greatly varying average firing rate of neurons in the network to efficiently allocate synaptic weights to an on-chip memory consisting of multiple non-uniformly sized memory banks. By assigning weights of frequently firing neurons to shallow, low-access cost memory and less actively accessed weights to deeper, high-density memories, the average power consumption of the synaptic weight memory is decreased without incurring a large area overhead. To benchmark our proposed architecture and find optimal configurations of memory arrangements, we perform an automatic exploration based on application requirements and hardware constraints. For memory designs synthesized in 28-nm CMOS technology, we show that our architecture can achieve a synaptic weight memory access power reduction of up to 61\% compared to a conventional design, with a 2.1$\times$ lower area overhead, as compared to a traditional uniformly partitioned memory bank that achieves a comparable reduction.