VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
2026-08-24 • Hardware Architecture
Hardware Architecture
AI summaryⓘ
The authors present VIPER, a fast and simple tool to predict how well Processing-in-Memory (PIM) designs will perform without running very slow simulations. VIPER combines real measurements of normal computer work with smart models of PIM behavior to quickly test many design options. It works for different types of PIM setups and considers factors like data transfer and memory limits, which many other tools miss. The authors tested VIPER against real systems and detailed simulators, showing it predicts performance quite accurately but much faster. Their studies also reveal important design trade-offs that simpler device-level methods overlook.
Processing-in-Memory (PIM)Design-space exploration (DSE)Host-PIM transferProcessing Near Memory (PNM)Processing Using Memory (PUM)Cycle-accurate simulationUPMEMDevice programming latencyArchitecture-aware performance modelingReRAM/FeFET crossbars
Authors
Haoran Geng, Tomas Sousa Pereira, Xiaoyang Lu, Xian-He Sun, Michael Niemier, X. Sharon Hu
Abstract
Processing-in-Memory (PIM) promises to reduce data movement overhead by executing computation in or near memory, but its realized application speedup remains highly design-dependent. Non-offloadable host execution, host-PIM transfers, limited PIM capacity, and device programming latency can limit end-to-end speedup, making fast early-stage design-space exploration (DSE) essential. However, existing PIM evaluation methods remain limited: circuit- and device-level tools cannot capture these end-to-end PIM performance factors, while cycle-accurate simulation is too slow for iterative DSE. To address this gap, we present VIPER, a unified, lightweight, and architecture-aware performance evaluation framework for PIM DSE. VIPER profiles host execution once and combines the measured host behavior with a PIM-aware analytical engine that sweeps PIM-side parameters across candidate designs. It supports both Processing Near Memory (PNM) and Processing Using Memory (PUM) under task-offloading and data-triggered execution by capturing host-PIM transfer, array access, in-memory computation, device programming latency, and capacity-induced partitioning, providing rapid architecture-aware performance estimates for iterative DSE without repeated cycle-accurate simulation. We validate VIPER against a commercial UPMEM system and more than 400 cycle-accurate gem5 configurations. VIPER predicts the UPMEM offloading decision and break-even region a priori, and, with a refined transfer model, captures the measured peak-and-rolloff behavior with 12\% mean speedup error across the DPU sweep (6\% up to the 256-DPU peak). Against gem5, VIPER achieves less than 10\% error while reducing evaluation time from hours to under one minute. Case studies of UPMEM, ReRAM/FeFET crossbars, and IMCRYPTO show that architecture-aware DSE reveals key performance trade-offs that device-level evaluation misses.