SYNTLOG: FSM Benchmarks Evaluation for FPGA
2026-08-24 • Hardware Architecture
Hardware Architecture
AI summaryⓘ
The authors created a set of 101 finite state machine (FSM) examples of various sizes to test how well different synthesis tools work. They compared their own tool, SYNTLOG, to Xilinx Vivado, looking at factors like speed, size, and logic depth of the circuits produced. SYNTLOG used fewer logic elements and produced shallower circuits in some modes, and it ran much faster than Vivado, especially for very large designs. Additionally, SYNTLOG includes built-in checks to ensure the circuits work correctly after synthesis. Vivado struggled to complete synthesis on the biggest examples within a reasonable time, while SYNTLOG finished quickly.
Finite State Machine (FSM)SynthesisTechnology MappingLookup Table (LUT)Logic LevelsRuntimeXilinx VivadoSYNTLOGArea OptimizationDelay Optimization
Authors
Samary Baranov, Danila Gorodecky
Abstract
We introduce a curated benchmark collection of \num{101} FSM descriptions organized into five size classes (\emph{small}, \emph{medium}, \emph{large}, \emph{huge}, \emph{super-huge}), spanning tens to thousands of states and up to hundreds of inputs and outputs. Using these benchmarks we compare an architecture-independent synthesis tool SYNTLOG against Xilinx Vivado at the synthesis (technology-mapping) level, under six optimization strategies. We compare three post-synthesis parameters: number of LUTs, number of logic levels, and runtime. SYNTLOG in area-driven mode uses substantially fewer LUTs than Vivado's area baseline at every size ($-45\%$ to $-66\%$), and its delay-driven mode is simultaneously shallower in logic depth than Vivado's default synthesis mode. SYNTLOG synthesis includes embedded functional validation. Runtime of SYNTLOG is faster by one to two orders of magnitude than Vivado synthesis. The proposed tool synthesizes and validates every \emph{huge} and \emph{super-huge} circuit in minutes, whereas Vivado fails to terminate on these designs after hours.