Effects of Hybrid CPU and Cache Architectures on Parallel HPC and Cloud Applications
2026-08-24 • Distributed, Parallel, and Cluster Computing
Distributed, Parallel, and Cluster Computing
AI summaryⓘ
The authors studied how new CPUs with two kinds of cores (big and small) and different cache layouts affect the performance of programs that run many tasks in parallel, especially in high-performance computing. They found that for programs where some tasks do more work than others, turning off strict thread-to-core assignment helps performance. Also, the new cache designs mostly don’t influence programs that share data unless those programs use locks to manage access. Their work helps understand how these hybrid CPUs affect program speed and will guide future research to improve performance and power use.
Hybrid CPU architectureAlderlakeParallel workloadsThread affinityWork imbalanceCache architectureHigh-performance computing (HPC)Thread scalingLocksShared data
Authors
Nanda Velugoti, Joseph Manzano, Nathan Tallent, Kyle Hale
Abstract
Hybrid CPU architectures have entered the mainstream desktop computing with the announcement of Intel's Alderlake architecture. Such a transition to heterogeneous CPU architecture has various performance and power implications on existing parallel workloads. In this paper we study the effects and impact of hybrid core and cache architecture on the performance of highly parallel HPC workloads. We also illustrate interesting thread scaling behavior for parallel workloads and describes the reason for such behavior both qualitatively and quantitatively. We also explore the impact of hybrid cache architecture on parallel shared data HPC applications. Finally, we illustrate that 1) parallel applications with work imbalance (i.e., threads in application perform different amount of work) scale better across hybrid cores when thread affinity is disabled and 2) hybrid cache architecture has very little impact on parallel shared data applications except for some workloads with locks. This work lays the foundation for our future work which focuses on extending this work to model parallel workloads and hybrid CPU architectures to improve their performance in terms of execution time, memory usage and power consumption.