Trusted Hardware Acceleration for Function Secret Sharing
2026-08-17 • Cryptography and Security
Cryptography and Security
AI summaryⓘ
The authors created a special hardware tool called the distributed function accelerator (DFA) to speed up a key step in privacy-focused computing called function secret sharing (FSS). This tool mainly helps generate and use distributed point functions (DPFs) much faster and with less energy. In one mode, DFA just speeds up part of the process without changing how it works, and in another mode, it also makes key creation local to reduce data moving around. Their tests show big improvements in speed, communication, and energy use for tasks like secure inference and private information retrieval. This makes privacy-preserving computing more practical by cutting down on overhead.
Function Secret SharingDistributed Point FunctionHardware AcceleratorSecure InferencePrivate Information RetrievalAES Pseudorandom Number GenerationKey GenerationCommunication OverheadEnergy EfficiencyData Movement
Authors
Pengzhi Huang, Kiwan Maeng, G. Edward Suh
Abstract
Function secret sharing (FSS) is a core building block for privacy-preserving systems such as secure inference and private information retrieval (PIR), but incurs significant overhead in key generation, communication, and data movement.We present the distributed function accelerator (DFA), a hardware accelerator that targets the dominant primitive in FSS: distributed point function (DPF) generation and evaluation. DFA combines a high-throughput fixed-function engine for AES-based pseudorandom number generation with a lightweight programmable unit for protocol-specific logic. In untrusted mode, DFA serves as a pure accelerator for DPF evaluation, improving throughput and energy efficiency without changing the protocol. In trusted mode, it further enables local, on-the-fly key generation, eliminating key distribution, and reducing storage and data movement overheads. Across representative workloads, DFA achieves a reduction of 10X end-to-end latency, a reduction of up to 20X communication and more than 5X energy savings for secure inference; and an improvement of 5X throughput and 10X energy reduction for PIR, with modest hardware cost.