RVANNS: Mixed-Precision Indexing and Locality-Aware Graph Traversal on RISC-V
2026-08-10 • Information Retrieval
Information Retrieval
AI summaryⓘ
The authors developed RVANNS, a system that improves how approximate nearest neighbor search (ANNS) runs on RISC-V vector CPUs. They created a new way to represent vectors in mixed precision to reduce overhead and designed a method to organize data so the computer can access it more efficiently. When tested, RVANNS ran much faster than previous methods on similar hardware and was also more power-efficient than some GPU approaches. Their work focuses on balancing speed, precision, and memory usage for better performance on these processors.
Approximate Nearest Neighbor Search (ANNS)RISC-V Vector Extension (RVV)Mixed-Precision ComputingGraph TraversalCache LocalityHNSW (Hierarchical Navigable Small World Graph)Vector ProcessingRegister GroupingThroughputQuantization
Authors
Chengying Huan, Yudong Liu, Jianguo Wang, Lizheng Chen, Renling Yin, Weijia Chen, Ji Qi, Jiageng Yu, Junjie Xu, Jie Zhang, Chen Tian, Yanjun Wu
Abstract
Approximate nearest neighbor search (ANNS) on CPUs is increasingly constrained by candidate-vector movement and decoding rather than peak arithmetic throughput. Although the RISC-V Vector Extension (RVV) provides vector-length-agnostic execution and LMUL-based register grouping, generic low-precision decoding still incurs conversion overhead, while irregular graph traversal generates scattered accesses that degrade cache locality and memory-level parallelism. We present RVANNS, an RVV-oriented ANNS engine that jointly optimizes vector representation and graph locality. Its Mixed-Precision Multi-Layer Index (MPMI) represents each vector with a dense 8-bit affine base and sparse FP16/FP32 residuals, fusing reconstruction with distance accumulation and aligning widening with LMUL-sized register groups. ROrder co-locates likely co-visited graph nodes and sorts remapped adjacency lists, transforming scattered payload probes into denser, predominantly forward-moving address streams. Integrated into Milvus, RVANNS achieves 3.39x and 4.94x speedups over scalar execution on real 128-bit and 256-bit RVV processors, respectively. Under controlled HNSW configurations, it improves throughput by 2.27--2.76x over RVV SIMD+FP32 and by 1.18--1.59x over the corresponding AVX-512 and SVE baselines. On Cohere10M, it further delivers 1.82--2.27x higher QPS/W than the evaluated GPU baselines.