Evaluating Forecasting Techniques for Hardware Errors on a Large-scale HPC System
2026-08-03 • Machine Learning
Machine Learning
AI summaryⓘ
The authors studied how well different methods can predict hardware errors in a supercomputer by looking at seven years of error logs. They found that prediction works better for errors that happen regularly and have consistent patterns, especially when using advanced models like LSTM and Transformer. However, errors that are rare or come in sudden bursts are much harder to predict. Their work offers advice on when forecasting hardware errors is likely to be successful and suggests ways to improve predictions in the future.
hardware error logshigh-performance computingtime series forecastingLSTMTransformer modelsstatistical modelsdeep learningerror predictionTheta supercomputertemporal features
Authors
Kaiyuan Liao, Xiwei Xuan, Tanwi Mallick, Kevin Brown, Christopher D. Carothers, Kwan-Liu Ma
Abstract
Hardware error logs in high-performance computing (HPC) systems provide early signals of abnormal behavior, yet there remain challenges in effectively forecasting these errors using modern predictive methods. This work investigates the boundaries of applying time series forecasting to HPC hardware error dynamics. We use seven years of production logs from the Theta supercomputer to evaluate the predictive efficacy of classical statistical and deep learning models. Our results show that forecasting effectiveness depends strongly on the temporal structure of the error series: regularly occurring and structurally stable errors can be modeled accurately, particularly by LSTM and Transformer architectures with temporal features, while sparse and burst-dominated errors remain difficult to predict. Rather than proposing a deployment-ready failure prediction framework, this study provides empirical guidance on when forecasting is effective and highlights potential directions for improving forecasting accuracy in HPC hardware error analysis.