DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation
2026-07-27 • Hardware Architecture
Hardware Architecture
AI summaryⓘ
The authors explain that building big computer chips with many cores is getting harder due to power and manufacturing limits. To fix this, chip design now splits chips into smaller parts called chiplets connected by very fast links. However, these links can have signal problems that affect performance, and current simulations often ignore these details. The authors created DICE, a tool inside a common simulator that models these signal issues and link behaviors more accurately to better predict real-world performance.
ChipletMulticore processorSignal integrityForward error correctionPHY (Physical layer)gem5 simulatorQC-LDPC encodingPAM4 modulationPacket retransmissionInter-chiplet communication
Authors
Rashid Aligholipour, Stefanos kaxiras, Yuan Yao
Abstract
Scaling monolithic multicores is increasingly constrained by power/thermal limits, yield, and rising manufacturing and testing costs. Chiplet designs address these challenges by partitioning large dies into smaller parts (typically multiple core-complex dies and an I/O die) linked via high-bandwidth physical fabrics (PHY). As bandwidth and wiring density scale, however, these short-reach links are pushed closer to their signal-integrity limits, increasing susceptibility to noise, crosstalk, and channel loss, motivating stronger link-level reliability mechanisms such as forward error correction (FEC). Despite this trend, state-of-the-art simulation infrastructures often approximate inter-chiplet links using oversimplified, fixed-latency models. Such abstractions overlook the inherently dynamic, runtime-dependent behavior of the PHY -- including channel conditions (e.g., signal-to-noise ratio shifts, signal crosstalk, clock jitter), iterative decoder convergence and packet retransmissions, and application dynamics (e.g., LLC-misses that travel across chiplet boundaries) -- all of which are hard to determine offline. We show that neglecting these effects distorts inter-chiplet packet-level timing and high-level performance metrics such as IPC, leading to off-trend simulation results. We present DICE, an in-simulation, runtime PHY modeling in gem5 that captures the end-to-end inter-chiplet datapath, including QC-LDPC encoding/decoding, PAM4 modulation, lossy-channel transmission, LLR-based demodulation, adaptive packet re-sending, and PHY-level flow control between chiplets.