Fixed Point Exploration For CV-QKD IR QC-MET-LDPC Toward Hardware Implementation
2026-07-20 • Hardware Architecture
Hardware ArchitectureInformation Theory
AI summaryⓘ
The authors studied different methods (SPA, MSA, NMS) for speeding up a certain kind of error correction used in quantum communication, focusing on fixed-point math to help hardware run faster. They tested how well these methods worked with various levels of number precision and found that the SPA method performed best overall. For simpler versions, a certain precision level (Q16.8) was needed to keep consistent results, where NMS worked better than MSA. In real-world use, SPA with a lower precision (Q8.4) gave the best mix of accuracy and hardware efficiency for big setups.
LDPC decodingCV-QKDfixed-point arithmeticSPAMSANMSFERquantizationlow-SNRhardware acceleration
Authors
Guilherme Vergne de Oliveira, Mauro Queiroz Nooblath Neto, Micael Andrade Dias, Francisco Revson Fernandes Pereira, Francisco Marcos de Assis, Valéria Loureiro da Silva, Nelson Alves Ferreira
Abstract
High-speed LDPC decoding is a major bottleneck in CV-QKD and motivates hardware acceleration with fixed-point arithmetic. This work compares SPA, MSA, and NMS under a unified low-SNR fixed-point framework using common graph, matrix, and quantization settings. Multiple formats are evaluated through FER, and average iterations. The results show that performance depends strongly on the interaction between decoder rule and numerical precision. SPA achieved the best overall performance. For reduced-complexity decoders, Q16.8 was the lowest consistent precision, with NMS outperforming MSA. Practically, SPA with Q8.4 offered the best balance between reliability and hardware efficiency for large-scale implementations.