SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor with Backend-Visible EP Context for Sustained Vector Throughput
2026-07-20 • Hardware Architecture
Hardware Architecture
AI summaryⓘ
The authors propose SEAM-V, a new way to improve how RISC-V vector processors handle instructions for data-parallel tasks like deep learning. Instead of the scalar core sending instructions one-by-one, SEAM-V uses a system that packs and streams multiple instructions together, reducing delays and enabling smarter execution. This design allows overlapping of work between instruction groups while managing dependencies and memory order safely. Their testing showed SEAM-V runs about 1.3 times faster on average compared to traditional methods, with some cases nearly tripling speed.
RISC-V Vector Extensionvector-length-agnosticdata-parallel workloadshybrid-decoupled vector executiontask-level decouplingvery long instruction word (VLIW)prefetchingdependence handlingRTL evaluationspeedup
Authors
Weiying Wang, Zhiwei Zhang
Abstract
Data-parallel workloads in deep learning and scientific computing continue to drive demand for higher processor throughput, energy efficiency, and scalability. The RISC-V Vector Extension (RVV) supports scalable execution through a vector-length-agnostic programming model. However, many tightly coupled implementations still rely on the scalar core to supply vector instructions one at a time, making execution susceptible to vector-instruction supply gaps, scalar-side progression delays, and conservative dependence handling in short-vector, loop-tail, and control/memory-interleaved phases. This paper presents SEAM-V, a hybrid-decoupled vector execution architecture for RVV. SEAM-V forms a continuous stream of execute packets (EPs) through task-level decoupling, local instruction supply, and VLIW-style packing. After an EP is serialized into individual requests, its EP identity and request-bound prefetch context remain visible to the dynamic vector backend, enabling same-EP candidate-hazard suppression and request-bound prefetching. The hybrid-dispatch path can also provide limited cross-EP vector overlap when the required safety conditions are satisfied. Cross-EP dependences, dependences not exempted by the EP contract, resource conflicts, and memory ordering remain dynamically managed by the backend. Cycle-accurate RTL evaluation shows that, compared with an Ara-based tightly coupled RVV implementation (TC), SEAM-V achieves a geometric-mean speedup of 1.34x across 17 representative kernels. The one-dimensional variable-AVL, BLAS and matrix, and fixed-size application groups achieve speedups of 1.50x, 1.25x, and 1.27x, respectively. At AVL=32, the geometric-mean speedup across six one-dimensional vector kernels approaches 3x.