SABLE: Minimalist Instruction-Level Authenticated Encryption for Constrained Confidential Computing
Cryptography and SecurityHardware ArchitectureEmerging Technologies
Summary
The authors present SABLE, a new RISC-V processor design that keeps instructions encrypted and verified while the CPU runs them, improving security without big changes to standard tools. Their design works with existing RISC-V toolchains by slightly modifying compiled programs and adds a step to decrypt and check instructions before execution. They test several versions of this concept on an FPGA, finding trade-offs between speed, power use, and resource needs. Their work shows how to balance these factors when adding instruction-level security to processors.
Authors
Hamid Noori, Carlton Shepherd
Abstract
Conventional processor designs expose code and data as plaintext throughout execution, rendering them inherently vulnerable to attacks that recover intellectual property or modify security/safety checks. Instruction-level encryption (ILE) enables CPU-level decryption, execution, and optionally authentication of individual encrypted program instructions at runtime. However, existing proposals depend on specific micro-architectures, detect corrupted instructions after they have executed, rely on non-standard ciphers, or require complex analyses of program state. In this work, we introduce and present a design exploration of a RISC-V processor architecture (SABLE) that enables minimally invasive instruction-level authenticated encryption of programs. SABLE is agnostic to the underlying micro-architecture, remaining compatible with the standard RISC-V toolchain with minor changes to post-process compiled ELF binaries. We integrate a decrypt-and-verify stage at two points (the instruction-memory wrapper and the CPU frontend) and explore seven ILE micro-architectures from a single-cycle (combinational) design to six multi-cycle (sequential) variants. We implement and evaluate the designs using ASCON-128a on a Xilinx Artix-7 FPGA with the open-source NEORV32 system on chip. Relative to baseline performance, the configurations span LUT, performance, power, and energy-per-instruction overheads of 1.6-9.3$\times$, 4.1-10.0$\times$, 1.5-8.0$\times$, and 10.4-80.0$\times$, respectively, using the Dhrystone benchmarking suite. Finally, we discuss design trade-offs, highlighting area-, performance-, and energy-aware design points.