CLDRoute: Conditional Latent Diffusion for Routability Map Generation in Physical Design
Machine Learning
Summary
The authors propose a new way to predict how easy it will be to route wires on a chip during its design. Instead of just giving one fixed prediction, their method creates multiple possible congestion and error maps, showing both the expected result and where predictions are less certain. Their approach uses special techniques to handle different types of problems like congestion and design rule violations. Testing on a benchmark shows their method produces accurate and informative predictions that can better guide chip design decisions early in the process.
Authors
Kiran Thorat, Nicole Meng, Caiwen Ding, Yingjie Lao, Zhijie Jerry Shi
Abstract
Accurate routability estimation during physical design is important for reducing costly post-routing iterations. Prior learning-based methods treat this task as deterministic prediction, mapping placement-stage features to a single congestion or DRC outcome. We instead formulate routability estimation as a conditional generation problem, where both routing congestion and DRC violations are modeled as spatially structured routability fields. Our framework, Conditional Latent Diffusion for Routeability estimation (CLDRoute), uses physics-aware conditioning and task-specific latent modeling to handle the different characteristics of congestion and DRC maps. This allows our method to supports sample-based inference, producing both a mean prediction and a spatial uncertainty estimate for the same input design. On CircuitNet 2.0 (N28), our method achieves, for DRC violation generation, an SSIM of 0.9678, an MAE of 0.0028, and a TopK@1% of 0.3494; for congestion generation, it achieves an SSIM of 0.9031, an MAE of 0.0286, and an NZ-Pearson of 0.3692. Overall, our framework provides a more practical view of routability at placement by generating both the expected outcome and its uncertainty.