From Patterns to Parsers: Automatic Generation of Efficient Hardware Parsers for FPGAs
Hardware Architecture
Summary
The authors created an open-source tool that turns easy-to-write parser descriptions into efficient hardware designs automatically. Their system separates the input description from the hardware code generation, producing readable and optimized SystemVerilog for different data widths. Unlike previous tools, theirs can handle complex pattern checks like ranges or negations, making it more flexible. They showed their tool works well for Ethernet parsing and network security, using fewer resources and running faster than older methods. This helps hardware designers quickly build custom parsers that work on many platforms.
Authors
Tushar Garg, Andrew Boutros
Abstract
This work presents an open-source tool for automatically generating efficient hardware parsers from high-level specifications. It uses a parsing intermediate representation (PIR) that decouples application-specific frontends from a common register-transfer level (RTL) generation backend. The backend produces optimized, human-readable SystemVerilog, handling FSM generation, byte-alignment, and multi-cycle field straddling for arbitrary datapath widths. The tool also extends pattern matching beyond simple equality checks by introducing custom symbolic tokens to support operations that existing parser generators cannot express, such as range validation, negation, and comparisons against external ports. We demonstrate two end-to-end flows using a P4 frontend for Ethernet protocol parsing and a Snort frontend for network intrusion detection, both using the same unmodified backend. The generated Ethernet parsers achieve up to 226% higher operating frequency and up to 97% fewer FPGA logic resources than prior work. A controlled synthetic study further shows that the tool's hierarchical pattern decomposition yields up to 8x resource utilization reduction over monolithic designs. Our open-source framework enables designers to rapidly implement high-performance, resource-efficient, vendor-agnostic hardware parsers for diverse applications.